2 * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those currently are:
7 * 440/460: 440SP/440SPe/460EX/460GT
9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
12 * (C) Copyright 2007-2009
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
15 * COPYRIGHT AMCC CORPORATION 2004
17 * SPDX-License-Identifier: GPL-2.0+
20 /* define DEBUG for debugging output (obviously ;-)) */
27 #include <asm/ppc4xx.h>
30 #include <asm/processor.h>
32 #include <asm/cache.h>
36 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
39 mfsdram(SDRAM_##mnemonic, data); \
40 printf("%20s[%02x] = 0x%08X\n", \
41 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
44 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
47 data = mfdcr(SDRAM_##mnemonic); \
48 printf("%20s[%02x] = 0x%08X\n", \
49 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
52 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
53 static void update_rdcc(void)
58 * Complete RDSS configuration as mentioned on page 7 of the AMCC
59 * PowerPC440SP/SPe DDR2 application note:
60 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
62 * Or item #10 "10. Complete RDSS configuration" in chapter
63 * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
66 mfsdram(SDRAM_RTSR, val);
67 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
68 mfsdram(SDRAM_RDCC, val);
69 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
71 mtsdram(SDRAM_RDCC, val);
77 #if defined(CONFIG_440)
79 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
80 * memory region. Right now the cache should still be disabled in U-Boot
81 * because of the EMAC driver, that need its buffer descriptor to be located
82 * in non cached memory.
84 * If at some time this restriction doesn't apply anymore, just define
85 * CONFIG_4xx_DCACHE in the board config file and this code should setup
86 * everything correctly.
88 #ifdef CONFIG_4xx_DCACHE
89 /* enable caching on SDRAM */
90 #define MY_TLB_WORD2_I_ENABLE 0
92 /* disable caching on SDRAM */
93 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
94 #endif /* CONFIG_4xx_DCACHE */
96 void dcbz_area(u32 start_address, u32 num_bytes);
97 #endif /* CONFIG_440 */
102 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
104 #if !defined(CONFIG_NAND_SPL)
105 /*-----------------------------------------------------------------------------+
107 *-----------------------------------------------------------------------------*/
108 phys_size_t sdram_memsize(void)
110 phys_size_t mem_size;
111 unsigned long mcopt2;
112 unsigned long mcstat;
119 mfsdram(SDRAM_MCOPT2, mcopt2);
120 mfsdram(SDRAM_MCSTAT, mcstat);
122 /* DDR controller must be enabled and not in self-refresh. */
123 /* Otherwise memsize is zero. */
124 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
125 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
126 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
127 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
128 for (i = 0; i < MAXBXCF; i++) {
129 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
131 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
132 #if defined(CONFIG_440)
133 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
135 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
138 case SDRAM_RXBAS_SDSZ_8:
141 case SDRAM_RXBAS_SDSZ_16:
144 case SDRAM_RXBAS_SDSZ_32:
147 case SDRAM_RXBAS_SDSZ_64:
150 case SDRAM_RXBAS_SDSZ_128:
153 case SDRAM_RXBAS_SDSZ_256:
156 case SDRAM_RXBAS_SDSZ_512:
159 case SDRAM_RXBAS_SDSZ_1024:
162 case SDRAM_RXBAS_SDSZ_2048:
165 case SDRAM_RXBAS_SDSZ_4096:
169 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
178 return mem_size << 20;
181 /*-----------------------------------------------------------------------------+
183 *-----------------------------------------------------------------------------*/
184 static unsigned long is_ecc_enabled(void)
188 mfsdram(SDRAM_MCOPT1, val);
190 return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
193 /*-----------------------------------------------------------------------------+
195 *-----------------------------------------------------------------------------*/
196 void board_add_ram_info(int use_default)
198 PPC4xx_SYS_INFO board_cfg;
201 if (is_ecc_enabled())
206 get_sys_info(&board_cfg);
208 #if defined(CONFIG_405EX)
209 val = board_cfg.freqPLB;
211 mfsdr(SDR0_DDR0, val);
212 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
214 printf(" enabled, %d MHz", (val * 2) / 1000000);
216 mfsdram(SDRAM_MMODE, val);
217 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
218 printf(", CL%d)", val);
220 #endif /* !CONFIG_NAND_SPL */
222 #if defined(CONFIG_SPD_EEPROM)
224 /*-----------------------------------------------------------------------------+
226 *-----------------------------------------------------------------------------*/
232 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
234 #define ONE_BILLION 1000000000
236 #define CMD_NOP (7 << 19)
237 #define CMD_PRECHARGE (2 << 19)
238 #define CMD_REFRESH (1 << 19)
239 #define CMD_EMR (0 << 19)
240 #define CMD_READ (5 << 19)
241 #define CMD_WRITE (4 << 19)
243 #define SELECT_MR (0 << 16)
244 #define SELECT_EMR (1 << 16)
245 #define SELECT_EMR2 (2 << 16)
246 #define SELECT_EMR3 (3 << 16)
249 #define DLL_RESET 0x00000100
251 #define WRITE_RECOV_2 (1 << 9)
252 #define WRITE_RECOV_3 (2 << 9)
253 #define WRITE_RECOV_4 (3 << 9)
254 #define WRITE_RECOV_5 (4 << 9)
255 #define WRITE_RECOV_6 (5 << 9)
257 #define BURST_LEN_4 0x00000002
260 #define ODT_0_OHM 0x00000000
261 #define ODT_50_OHM 0x00000044
262 #define ODT_75_OHM 0x00000004
263 #define ODT_150_OHM 0x00000040
265 #define ODS_FULL 0x00000000
266 #define ODS_REDUCED 0x00000002
267 #define OCD_CALIB_DEF 0x00000380
269 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
270 #define ODT_EB0R (0x80000000 >> 8)
271 #define ODT_EB0W (0x80000000 >> 7)
272 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
273 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
274 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
276 /* Defines for the Read Cycle Delay test */
277 #define NUMMEMTESTS 8
278 #define NUMMEMWORDS 8
279 #define NUMLOOPS 64 /* memory test loops */
282 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
283 * To support such configurations, we "only" map the first 2GB via the TLB's. We
284 * need some free virtual address space for the remaining peripherals like, SoC
285 * devices, FLASH etc.
287 * Note that ECC is currently not supported on configurations with more than 2GB
288 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
289 * the ECC parity byte of the remaining area can't be written.
293 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
295 void __spd_ddr_init_hang (void)
299 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
302 * To provide an interface for board specific config values in this common
303 * DDR setup code, we implement he "weak" default functions here. They return
304 * the default value back to the caller.
306 * Please see include/configs/yucca.h for an example fora board specific
309 u32 __ddr_wrdtr(u32 default_val)
313 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
315 u32 __ddr_clktr(u32 default_val)
319 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
322 /* Private Structure Definitions */
324 /* enum only to ease code for cas latency setting */
325 typedef enum ddr_cas_id {
333 /*-----------------------------------------------------------------------------+
335 *-----------------------------------------------------------------------------*/
336 static void get_spd_info(unsigned long *dimm_populated,
337 unsigned char *iic0_dimm_addr,
338 unsigned long num_dimm_banks);
339 static void check_mem_type(unsigned long *dimm_populated,
340 unsigned char *iic0_dimm_addr,
341 unsigned long num_dimm_banks);
342 static void check_frequency(unsigned long *dimm_populated,
343 unsigned char *iic0_dimm_addr,
344 unsigned long num_dimm_banks);
345 static void check_rank_number(unsigned long *dimm_populated,
346 unsigned char *iic0_dimm_addr,
347 unsigned long num_dimm_banks);
348 static void check_voltage_type(unsigned long *dimm_populated,
349 unsigned char *iic0_dimm_addr,
350 unsigned long num_dimm_banks);
351 static void program_memory_queue(unsigned long *dimm_populated,
352 unsigned char *iic0_dimm_addr,
353 unsigned long num_dimm_banks);
354 static void program_codt(unsigned long *dimm_populated,
355 unsigned char *iic0_dimm_addr,
356 unsigned long num_dimm_banks);
357 static void program_mode(unsigned long *dimm_populated,
358 unsigned char *iic0_dimm_addr,
359 unsigned long num_dimm_banks,
360 ddr_cas_id_t *selected_cas,
361 int *write_recovery);
362 static void program_tr(unsigned long *dimm_populated,
363 unsigned char *iic0_dimm_addr,
364 unsigned long num_dimm_banks);
365 static void program_rtr(unsigned long *dimm_populated,
366 unsigned char *iic0_dimm_addr,
367 unsigned long num_dimm_banks);
368 static void program_bxcf(unsigned long *dimm_populated,
369 unsigned char *iic0_dimm_addr,
370 unsigned long num_dimm_banks);
371 static void program_copt1(unsigned long *dimm_populated,
372 unsigned char *iic0_dimm_addr,
373 unsigned long num_dimm_banks);
374 static void program_initplr(unsigned long *dimm_populated,
375 unsigned char *iic0_dimm_addr,
376 unsigned long num_dimm_banks,
377 ddr_cas_id_t selected_cas,
379 #ifdef CONFIG_DDR_ECC
380 static void program_ecc(unsigned long *dimm_populated,
381 unsigned char *iic0_dimm_addr,
382 unsigned long num_dimm_banks,
383 unsigned long tlb_word2_i_value);
385 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
386 static void program_DQS_calibration(unsigned long *dimm_populated,
387 unsigned char *iic0_dimm_addr,
388 unsigned long num_dimm_banks);
389 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
390 static void test(void);
392 static void DQS_calibration_process(void);
396 static unsigned char spd_read(uchar chip, uint addr)
398 unsigned char data[2];
400 if (i2c_probe(chip) == 0)
401 if (i2c_read(chip, addr, 1, data, 1) == 0)
407 /*-----------------------------------------------------------------------------+
408 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
409 * Note: This routine runs from flash with a stack set up in the chip's
410 * sram space. It is important that the routine does not require .sbss, .bss or
411 * .data sections. It also cannot call routines that require these sections.
412 *-----------------------------------------------------------------------------*/
413 /*-----------------------------------------------------------------------------
415 * Description: Configures SDRAM memory banks for DDR operation.
416 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
417 * via the IIC bus and then configures the DDR SDRAM memory
418 * banks appropriately. If Auto Memory Configuration is
419 * not used, it is assumed that no DIMM is plugged
420 *-----------------------------------------------------------------------------*/
421 phys_size_t initdram(int board_type)
423 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
424 unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
425 unsigned long num_dimm_banks; /* on board dimm banks */
427 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
429 phys_size_t dram_size = 0;
431 num_dimm_banks = sizeof(iic0_dimm_addr);
433 /*------------------------------------------------------------------
434 * Reset the DDR-SDRAM controller.
435 *-----------------------------------------------------------------*/
436 mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
437 mtsdr(SDR0_SRST, 0x00000000);
440 * Make sure I2C controller is initialized
444 /* switch to correct I2C bus */
445 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
446 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
448 /*------------------------------------------------------------------
449 * Clear out the serial presence detect buffers.
450 * Perform IIC reads from the dimm. Fill in the spds.
451 * Check to see if the dimm slots are populated
452 *-----------------------------------------------------------------*/
453 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
455 /*------------------------------------------------------------------
456 * Check the memory type for the dimms plugged.
457 *-----------------------------------------------------------------*/
458 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
460 /*------------------------------------------------------------------
461 * Check the frequency supported for the dimms plugged.
462 *-----------------------------------------------------------------*/
463 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
465 /*------------------------------------------------------------------
466 * Check the total rank number.
467 *-----------------------------------------------------------------*/
468 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
470 /*------------------------------------------------------------------
471 * Check the voltage type for the dimms plugged.
472 *-----------------------------------------------------------------*/
473 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
475 /*------------------------------------------------------------------
476 * Program SDRAM controller options 2 register
477 * Except Enabling of the memory controller.
478 *-----------------------------------------------------------------*/
479 mfsdram(SDRAM_MCOPT2, val);
480 mtsdram(SDRAM_MCOPT2,
482 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
483 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
484 SDRAM_MCOPT2_ISIE_MASK))
485 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
486 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
487 SDRAM_MCOPT2_ISIE_ENABLE));
489 /*------------------------------------------------------------------
490 * Program SDRAM controller options 1 register
491 * Note: Does not enable the memory controller.
492 *-----------------------------------------------------------------*/
493 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
495 /*------------------------------------------------------------------
496 * Set the SDRAM Controller On Die Termination Register
497 *-----------------------------------------------------------------*/
498 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
500 /*------------------------------------------------------------------
501 * Program SDRAM refresh register.
502 *-----------------------------------------------------------------*/
503 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
505 /*------------------------------------------------------------------
506 * Program SDRAM mode register.
507 *-----------------------------------------------------------------*/
508 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
509 &selected_cas, &write_recovery);
511 /*------------------------------------------------------------------
512 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
513 *-----------------------------------------------------------------*/
514 mfsdram(SDRAM_WRDTR, val);
515 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
516 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
518 /*------------------------------------------------------------------
519 * Set the SDRAM Clock Timing Register
520 *-----------------------------------------------------------------*/
521 mfsdram(SDRAM_CLKTR, val);
522 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
523 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
525 /*------------------------------------------------------------------
526 * Program the BxCF registers.
527 *-----------------------------------------------------------------*/
528 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
530 /*------------------------------------------------------------------
531 * Program SDRAM timing registers.
532 *-----------------------------------------------------------------*/
533 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
535 /*------------------------------------------------------------------
536 * Set the Extended Mode register
537 *-----------------------------------------------------------------*/
538 mfsdram(SDRAM_MEMODE, val);
539 mtsdram(SDRAM_MEMODE,
540 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
541 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
542 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
543 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
545 /*------------------------------------------------------------------
546 * Program Initialization preload registers.
547 *-----------------------------------------------------------------*/
548 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
549 selected_cas, write_recovery);
551 /*------------------------------------------------------------------
552 * Delay to ensure 200usec have elapsed since reset.
553 *-----------------------------------------------------------------*/
556 /*------------------------------------------------------------------
557 * Set the memory queue core base addr.
558 *-----------------------------------------------------------------*/
559 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
561 /*------------------------------------------------------------------
562 * Program SDRAM controller options 2 register
563 * Enable the memory controller.
564 *-----------------------------------------------------------------*/
565 mfsdram(SDRAM_MCOPT2, val);
566 mtsdram(SDRAM_MCOPT2,
567 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
568 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
569 SDRAM_MCOPT2_IPTR_EXECUTE);
571 /*------------------------------------------------------------------
572 * Wait for IPTR_EXECUTE init sequence to complete.
573 *-----------------------------------------------------------------*/
575 mfsdram(SDRAM_MCSTAT, val);
576 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
578 /* enable the controller only after init sequence completes */
579 mfsdram(SDRAM_MCOPT2, val);
580 mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
582 /* Make sure delay-line calibration is done before proceeding */
584 mfsdram(SDRAM_DLCR, val);
585 } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
587 /* get installed memory size */
588 dram_size = sdram_memsize();
593 if (dram_size > CONFIG_MAX_MEM_MAPPED)
594 dram_size = CONFIG_MAX_MEM_MAPPED;
596 /* and program tlb entries for this size (dynamic) */
599 * Program TLB entries with caches enabled, for best performace
600 * while auto-calibrating and ECC generation
602 program_tlb(0, 0, dram_size, 0);
604 /*------------------------------------------------------------------
606 *-----------------------------------------------------------------*/
607 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
608 DQS_autocalibration();
610 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
613 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
614 * PowerPC440SP/SPe DDR2 application note:
615 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
619 #ifdef CONFIG_DDR_ECC
620 /*------------------------------------------------------------------
621 * If ecc is enabled, initialize the parity bits.
622 *-----------------------------------------------------------------*/
623 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
627 * Flush the dcache before removing the TLB with caches
628 * enabled. Otherwise this might lead to problems later on,
629 * e.g. while booting Linux (as seen on ICON-440SPe).
634 * Now after initialization (auto-calibration and ECC generation)
635 * remove the TLB entries with caches enabled and program again with
636 * desired cache functionality
638 remove_tlb(0, dram_size);
639 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
641 ppc4xx_ibm_ddr2_register_dump();
644 * Clear potential errors resulting from auto-calibration.
645 * If not done, then we could get an interrupt later on when
646 * exceptions are enabled.
648 set_mcsr(get_mcsr());
650 return sdram_memsize();
653 static void get_spd_info(unsigned long *dimm_populated,
654 unsigned char *iic0_dimm_addr,
655 unsigned long num_dimm_banks)
657 unsigned long dimm_num;
658 unsigned long dimm_found;
659 unsigned char num_of_bytes;
660 unsigned char total_size;
663 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
667 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
668 debug("\nspd_read(0x%x) returned %d\n",
669 iic0_dimm_addr[dimm_num], num_of_bytes);
670 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
671 debug("spd_read(0x%x) returned %d\n",
672 iic0_dimm_addr[dimm_num], total_size);
674 if ((num_of_bytes != 0) && (total_size != 0)) {
675 dimm_populated[dimm_num] = true;
677 debug("DIMM slot %lu: populated\n", dimm_num);
679 dimm_populated[dimm_num] = false;
680 debug("DIMM slot %lu: Not populated\n", dimm_num);
684 if (dimm_found == false) {
685 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
686 spd_ddr_init_hang ();
691 /*------------------------------------------------------------------
692 * For the memory DIMMs installed, this routine verifies that they
693 * really are DDR specific DIMMs.
694 *-----------------------------------------------------------------*/
695 static void check_mem_type(unsigned long *dimm_populated,
696 unsigned char *iic0_dimm_addr,
697 unsigned long num_dimm_banks)
699 unsigned long dimm_num;
700 unsigned long dimm_type;
702 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
703 if (dimm_populated[dimm_num] == true) {
704 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
707 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
708 "slot %d.\n", (unsigned int)dimm_num);
709 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
710 printf("Replace the DIMM module with a supported DIMM.\n\n");
711 spd_ddr_init_hang ();
714 printf("ERROR: EDO DIMM detected in slot %d.\n",
715 (unsigned int)dimm_num);
716 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
717 printf("Replace the DIMM module with a supported DIMM.\n\n");
718 spd_ddr_init_hang ();
721 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
722 (unsigned int)dimm_num);
723 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
724 printf("Replace the DIMM module with a supported DIMM.\n\n");
725 spd_ddr_init_hang ();
728 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
729 (unsigned int)dimm_num);
730 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
731 printf("Replace the DIMM module with a supported DIMM.\n\n");
732 spd_ddr_init_hang ();
735 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
736 (unsigned int)dimm_num);
737 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
738 printf("Replace the DIMM module with a supported DIMM.\n\n");
739 spd_ddr_init_hang ();
742 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
743 (unsigned int)dimm_num);
744 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
745 printf("Replace the DIMM module with a supported DIMM.\n\n");
746 spd_ddr_init_hang ();
749 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
750 dimm_populated[dimm_num] = SDRAM_DDR1;
753 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
754 dimm_populated[dimm_num] = SDRAM_DDR2;
757 printf("ERROR: Unknown DIMM detected in slot %d.\n",
758 (unsigned int)dimm_num);
759 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
760 printf("Replace the DIMM module with a supported DIMM.\n\n");
761 spd_ddr_init_hang ();
766 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
767 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
768 && (dimm_populated[dimm_num] != SDRAM_NONE)
769 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
770 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
771 spd_ddr_init_hang ();
776 /*------------------------------------------------------------------
777 * For the memory DIMMs installed, this routine verifies that
778 * frequency previously calculated is supported.
779 *-----------------------------------------------------------------*/
780 static void check_frequency(unsigned long *dimm_populated,
781 unsigned char *iic0_dimm_addr,
782 unsigned long num_dimm_banks)
784 unsigned long dimm_num;
785 unsigned long tcyc_reg;
786 unsigned long cycle_time;
787 unsigned long calc_cycle_time;
788 unsigned long sdram_freq;
789 unsigned long sdr_ddrpll;
790 PPC4xx_SYS_INFO board_cfg;
792 /*------------------------------------------------------------------
793 * Get the board configuration info.
794 *-----------------------------------------------------------------*/
795 get_sys_info(&board_cfg);
797 mfsdr(SDR0_DDR0, sdr_ddrpll);
798 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
801 * calc_cycle_time is calculated from DDR frequency set by board/chip
802 * and is expressed in multiple of 10 picoseconds
803 * to match the way DIMM cycle time is calculated below.
805 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
807 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
808 if (dimm_populated[dimm_num] != SDRAM_NONE) {
809 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
811 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
812 * the higher order nibble (bits 4-7) designates the cycle time
813 * to a granularity of 1ns;
814 * the value presented by the lower order nibble (bits 0-3)
815 * has a granularity of .1ns and is added to the value designated
816 * by the higher nibble. In addition, four lines of the lower order
817 * nibble are assigned to support +.25,+.33, +.66 and +.75.
819 /* Convert from hex to decimal */
820 if ((tcyc_reg & 0x0F) == 0x0D)
821 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
822 else if ((tcyc_reg & 0x0F) == 0x0C)
823 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
824 else if ((tcyc_reg & 0x0F) == 0x0B)
825 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
826 else if ((tcyc_reg & 0x0F) == 0x0A)
827 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
829 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
830 ((tcyc_reg & 0x0F)*10);
831 debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
833 if (cycle_time > (calc_cycle_time + 10)) {
835 * the provided sdram cycle_time is too small
836 * for the available DIMM cycle_time.
837 * The additionnal 100ps is here to accept a small incertainty.
839 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
840 "slot %d \n while calculated cycle time is %d ps.\n",
841 (unsigned int)(cycle_time*10),
842 (unsigned int)dimm_num,
843 (unsigned int)(calc_cycle_time*10));
844 printf("Replace the DIMM, or change DDR frequency via "
845 "strapping bits.\n\n");
846 spd_ddr_init_hang ();
852 /*------------------------------------------------------------------
853 * For the memory DIMMs installed, this routine verifies two
854 * ranks/banks maximum are availables.
855 *-----------------------------------------------------------------*/
856 static void check_rank_number(unsigned long *dimm_populated,
857 unsigned char *iic0_dimm_addr,
858 unsigned long num_dimm_banks)
860 unsigned long dimm_num;
861 unsigned long dimm_rank;
862 unsigned long total_rank = 0;
864 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
865 if (dimm_populated[dimm_num] != SDRAM_NONE) {
866 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
867 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
868 dimm_rank = (dimm_rank & 0x0F) +1;
870 dimm_rank = dimm_rank & 0x0F;
873 if (dimm_rank > MAXRANKS) {
874 printf("ERROR: DRAM DIMM detected with %lu ranks in "
875 "slot %lu is not supported.\n", dimm_rank, dimm_num);
876 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
877 printf("Replace the DIMM module with a supported DIMM.\n\n");
878 spd_ddr_init_hang ();
880 total_rank += dimm_rank;
882 if (total_rank > MAXRANKS) {
883 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
884 "for all slots.\n", (unsigned int)total_rank);
885 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
886 printf("Remove one of the DIMM modules.\n\n");
887 spd_ddr_init_hang ();
892 /*------------------------------------------------------------------
893 * only support 2.5V modules.
894 * This routine verifies this.
895 *-----------------------------------------------------------------*/
896 static void check_voltage_type(unsigned long *dimm_populated,
897 unsigned char *iic0_dimm_addr,
898 unsigned long num_dimm_banks)
900 unsigned long dimm_num;
901 unsigned long voltage_type;
903 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
904 if (dimm_populated[dimm_num] != SDRAM_NONE) {
905 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
906 switch (voltage_type) {
908 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
909 printf("This DIMM is 5.0 Volt/TTL.\n");
910 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
911 (unsigned int)dimm_num);
912 spd_ddr_init_hang ();
915 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
916 printf("This DIMM is LVTTL.\n");
917 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
918 (unsigned int)dimm_num);
919 spd_ddr_init_hang ();
922 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
923 printf("This DIMM is 1.5 Volt.\n");
924 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
925 (unsigned int)dimm_num);
926 spd_ddr_init_hang ();
929 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
930 printf("This DIMM is 3.3 Volt/TTL.\n");
931 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
932 (unsigned int)dimm_num);
933 spd_ddr_init_hang ();
936 /* 2.5 Voltage only for DDR1 */
939 /* 1.8 Voltage only for DDR2 */
942 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
943 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
944 (unsigned int)dimm_num);
945 spd_ddr_init_hang ();
952 /*-----------------------------------------------------------------------------+
954 *-----------------------------------------------------------------------------*/
955 static void program_copt1(unsigned long *dimm_populated,
956 unsigned char *iic0_dimm_addr,
957 unsigned long num_dimm_banks)
959 unsigned long dimm_num;
960 unsigned long mcopt1;
961 unsigned long ecc_enabled;
962 unsigned long ecc = 0;
963 unsigned long data_width = 0;
964 unsigned long dimm_32bit;
965 unsigned long dimm_64bit;
966 unsigned long registered = 0;
967 unsigned long attribute = 0;
968 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
969 unsigned long bankcount;
972 #ifdef CONFIG_DDR_ECC
982 /*------------------------------------------------------------------
983 * Set memory controller options reg 1, SDRAM_MCOPT1.
984 *-----------------------------------------------------------------*/
985 mfsdram(SDRAM_MCOPT1, val);
986 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
987 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
988 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
989 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
990 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
991 SDRAM_MCOPT1_DREF_MASK);
993 mcopt1 |= SDRAM_MCOPT1_QDEP;
994 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
995 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
996 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
997 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
998 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1000 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1001 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1002 /* test ecc support */
1003 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1004 if (ecc != 0x02) /* ecc not supported */
1005 ecc_enabled = false;
1007 /* test bank count */
1008 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1009 if (bankcount == 0x04) /* bank count = 4 */
1010 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1011 else /* bank count = 8 */
1012 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1014 /* test for buffered/unbuffered, registered, differential clocks */
1015 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1016 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1018 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1019 if (dimm_num == 0) {
1020 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1021 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1022 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1023 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1024 if (registered == 1) { /* DDR2 always buffered */
1025 /* TODO: what about above comments ? */
1026 mcopt1 |= SDRAM_MCOPT1_RDEN;
1029 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1030 if ((attribute & 0x02) == 0x00) {
1031 /* buffered not supported */
1034 mcopt1 |= SDRAM_MCOPT1_RDEN;
1039 else if (dimm_num == 1) {
1040 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1041 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1042 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1043 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1044 if (registered == 1) {
1045 /* DDR2 always buffered */
1046 mcopt1 |= SDRAM_MCOPT1_RDEN;
1049 if ((attribute & 0x02) == 0x00) {
1050 /* buffered not supported */
1053 mcopt1 |= SDRAM_MCOPT1_RDEN;
1059 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1060 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1061 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1063 switch (data_width) {
1073 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1075 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1081 /* verify matching properties */
1082 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1084 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1085 spd_ddr_init_hang ();
1089 if ((dimm_64bit == true) && (dimm_32bit == true)) {
1090 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1091 spd_ddr_init_hang ();
1092 } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
1093 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1094 } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
1095 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1097 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1098 spd_ddr_init_hang ();
1101 if (ecc_enabled == true)
1102 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1104 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1106 mtsdram(SDRAM_MCOPT1, mcopt1);
1109 /*-----------------------------------------------------------------------------+
1111 *-----------------------------------------------------------------------------*/
1112 static void program_codt(unsigned long *dimm_populated,
1113 unsigned char *iic0_dimm_addr,
1114 unsigned long num_dimm_banks)
1117 unsigned long modt0 = 0;
1118 unsigned long modt1 = 0;
1119 unsigned long modt2 = 0;
1120 unsigned long modt3 = 0;
1121 unsigned char dimm_num;
1122 unsigned char dimm_rank;
1123 unsigned char total_rank = 0;
1124 unsigned char total_dimm = 0;
1125 unsigned char dimm_type = 0;
1126 unsigned char firstSlot = 0;
1128 /*------------------------------------------------------------------
1129 * Set the SDRAM Controller On Die Termination Register
1130 *-----------------------------------------------------------------*/
1131 mfsdram(SDRAM_CODT, codt);
1132 codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1133 codt |= SDRAM_CODT_IO_NMODE;
1135 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1136 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1137 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1138 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1139 dimm_rank = (dimm_rank & 0x0F) + 1;
1140 dimm_type = SDRAM_DDR2;
1142 dimm_rank = dimm_rank & 0x0F;
1143 dimm_type = SDRAM_DDR1;
1146 total_rank += dimm_rank;
1148 if ((dimm_num == 0) && (total_dimm == 1))
1154 if (dimm_type == SDRAM_DDR2) {
1155 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1156 if ((total_dimm == 1) && (firstSlot == true)) {
1157 if (total_rank == 1) { /* PUUU */
1158 codt |= CALC_ODT_R(0);
1159 modt0 = CALC_ODT_W(0);
1164 if (total_rank == 2) { /* PPUU */
1165 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1166 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1171 } else if ((total_dimm == 1) && (firstSlot != true)) {
1172 if (total_rank == 1) { /* UUPU */
1173 codt |= CALC_ODT_R(2);
1176 modt2 = CALC_ODT_W(2);
1179 if (total_rank == 2) { /* UUPP */
1180 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1183 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1187 if (total_dimm == 2) {
1188 if (total_rank == 2) { /* PUPU */
1189 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1190 modt0 = CALC_ODT_RW(2);
1192 modt2 = CALC_ODT_RW(0);
1195 if (total_rank == 4) { /* PPPP */
1196 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1197 CALC_ODT_R(2) | CALC_ODT_R(3);
1198 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1200 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1205 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1211 if (total_dimm == 1) {
1212 if (total_rank == 1)
1214 if (total_rank == 2)
1217 if (total_dimm == 2) {
1218 if (total_rank == 2)
1220 if (total_rank == 4)
1225 debug("nb of dimm %d\n", total_dimm);
1226 debug("nb of rank %d\n", total_rank);
1227 if (total_dimm == 1)
1228 debug("dimm in slot %d\n", firstSlot);
1230 mtsdram(SDRAM_CODT, codt);
1231 mtsdram(SDRAM_MODT0, modt0);
1232 mtsdram(SDRAM_MODT1, modt1);
1233 mtsdram(SDRAM_MODT2, modt2);
1234 mtsdram(SDRAM_MODT3, modt3);
1237 /*-----------------------------------------------------------------------------+
1239 *-----------------------------------------------------------------------------*/
1240 static void program_initplr(unsigned long *dimm_populated,
1241 unsigned char *iic0_dimm_addr,
1242 unsigned long num_dimm_banks,
1243 ddr_cas_id_t selected_cas,
1257 /******************************************************
1258 ** Assumption: if more than one DIMM, all DIMMs are the same
1259 ** as already checked in check_memory_type
1260 ******************************************************/
1262 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1263 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1264 mtsdram(SDRAM_INITPLR1, 0x81900400);
1265 mtsdram(SDRAM_INITPLR2, 0x81810000);
1266 mtsdram(SDRAM_INITPLR3, 0xff800162);
1267 mtsdram(SDRAM_INITPLR4, 0x81900400);
1268 mtsdram(SDRAM_INITPLR5, 0x86080000);
1269 mtsdram(SDRAM_INITPLR6, 0x86080000);
1270 mtsdram(SDRAM_INITPLR7, 0x81000062);
1271 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1272 switch (selected_cas) {
1283 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1284 spd_ddr_init_hang ();
1290 * ToDo - Still a problem with the write recovery:
1291 * On the Corsair CM2X512-5400C4 module, setting write recovery
1292 * in the INITPLR reg to the value calculated in program_mode()
1293 * results in not correctly working DDR2 memory (crash after
1296 * So for now, set the write recovery to 3. This seems to work
1297 * on the Corair module too.
1301 switch (write_recovery) {
1315 printf("ERROR: write recovery not support (%d)", write_recovery);
1316 spd_ddr_init_hang ();
1320 wr = WRITE_RECOV_3; /* test-only, see description above */
1323 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1324 if (dimm_populated[dimm_num] != SDRAM_NONE)
1326 if (total_dimm == 1) {
1329 } else if (total_dimm == 2) {
1333 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1334 spd_ddr_init_hang ();
1337 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1338 emr = CMD_EMR | SELECT_EMR | odt | ods;
1339 emr2 = CMD_EMR | SELECT_EMR2;
1340 emr3 = CMD_EMR | SELECT_EMR3;
1341 /* NOP - Wait 106 MemClk cycles */
1342 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1343 SDRAM_INITPLR_IMWT_ENCODE(106));
1345 /* precharge 4 MemClk cycles */
1346 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1347 SDRAM_INITPLR_IMWT_ENCODE(4));
1348 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1349 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1350 SDRAM_INITPLR_IMWT_ENCODE(2));
1351 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1352 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1353 SDRAM_INITPLR_IMWT_ENCODE(2));
1354 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1355 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1356 SDRAM_INITPLR_IMWT_ENCODE(2));
1357 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1358 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1359 SDRAM_INITPLR_IMWT_ENCODE(200));
1361 /* precharge 4 MemClk cycles */
1362 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1363 SDRAM_INITPLR_IMWT_ENCODE(4));
1364 /* Refresh 25 MemClk cycles */
1365 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1366 SDRAM_INITPLR_IMWT_ENCODE(25));
1367 /* Refresh 25 MemClk cycles */
1368 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1369 SDRAM_INITPLR_IMWT_ENCODE(25));
1370 /* Refresh 25 MemClk cycles */
1371 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1372 SDRAM_INITPLR_IMWT_ENCODE(25));
1373 /* Refresh 25 MemClk cycles */
1374 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1375 SDRAM_INITPLR_IMWT_ENCODE(25));
1376 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1377 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1378 SDRAM_INITPLR_IMWT_ENCODE(2));
1379 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1380 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1381 SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1383 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1384 SDRAM_INITPLR_IMWT_ENCODE(2));
1386 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1387 spd_ddr_init_hang ();
1391 /*------------------------------------------------------------------
1392 * This routine programs the SDRAM_MMODE register.
1393 * the selected_cas is an output parameter, that will be passed
1394 * by caller to call the above program_initplr( )
1395 *-----------------------------------------------------------------*/
1396 static void program_mode(unsigned long *dimm_populated,
1397 unsigned char *iic0_dimm_addr,
1398 unsigned long num_dimm_banks,
1399 ddr_cas_id_t *selected_cas,
1400 int *write_recovery)
1402 unsigned long dimm_num;
1403 unsigned long sdram_ddr1;
1404 unsigned long t_wr_ns;
1405 unsigned long t_wr_clk;
1406 unsigned long cas_bit;
1407 unsigned long cas_index;
1408 unsigned long sdram_freq;
1409 unsigned long ddr_check;
1410 unsigned long mmode;
1411 unsigned long tcyc_reg;
1412 unsigned long cycle_2_0_clk;
1413 unsigned long cycle_2_5_clk;
1414 unsigned long cycle_3_0_clk;
1415 unsigned long cycle_4_0_clk;
1416 unsigned long cycle_5_0_clk;
1417 unsigned long max_2_0_tcyc_ns_x_100;
1418 unsigned long max_2_5_tcyc_ns_x_100;
1419 unsigned long max_3_0_tcyc_ns_x_100;
1420 unsigned long max_4_0_tcyc_ns_x_100;
1421 unsigned long max_5_0_tcyc_ns_x_100;
1422 unsigned long cycle_time_ns_x_100[3];
1423 PPC4xx_SYS_INFO board_cfg;
1424 unsigned char cas_2_0_available;
1425 unsigned char cas_2_5_available;
1426 unsigned char cas_3_0_available;
1427 unsigned char cas_4_0_available;
1428 unsigned char cas_5_0_available;
1429 unsigned long sdr_ddrpll;
1431 /*------------------------------------------------------------------
1432 * Get the board configuration info.
1433 *-----------------------------------------------------------------*/
1434 get_sys_info(&board_cfg);
1436 mfsdr(SDR0_DDR0, sdr_ddrpll);
1437 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1438 debug("sdram_freq=%lu\n", sdram_freq);
1440 /*------------------------------------------------------------------
1441 * Handle the timing. We need to find the worst case timing of all
1442 * the dimm modules installed.
1443 *-----------------------------------------------------------------*/
1445 cas_2_0_available = true;
1446 cas_2_5_available = true;
1447 cas_3_0_available = true;
1448 cas_4_0_available = true;
1449 cas_5_0_available = true;
1450 max_2_0_tcyc_ns_x_100 = 10;
1451 max_2_5_tcyc_ns_x_100 = 10;
1452 max_3_0_tcyc_ns_x_100 = 10;
1453 max_4_0_tcyc_ns_x_100 = 10;
1454 max_5_0_tcyc_ns_x_100 = 10;
1457 /* loop through all the DIMM slots on the board */
1458 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1459 /* If a dimm is installed in a particular slot ... */
1460 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1461 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1466 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1467 debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1469 /* For a particular DIMM, grab the three CAS values it supports */
1470 for (cas_index = 0; cas_index < 3; cas_index++) {
1471 switch (cas_index) {
1473 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1476 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1479 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1483 if ((tcyc_reg & 0x0F) >= 10) {
1484 if ((tcyc_reg & 0x0F) == 0x0D) {
1485 /* Convert from hex to decimal */
1486 cycle_time_ns_x_100[cas_index] =
1487 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1489 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1490 "in slot %d\n", (unsigned int)dimm_num);
1491 spd_ddr_init_hang ();
1494 /* Convert from hex to decimal */
1495 cycle_time_ns_x_100[cas_index] =
1496 (((tcyc_reg & 0xF0) >> 4) * 100) +
1497 ((tcyc_reg & 0x0F)*10);
1499 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1500 cycle_time_ns_x_100[cas_index]);
1503 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1504 /* supported for a particular DIMM. */
1509 * DDR devices use the following bitmask for CAS latency:
1510 * Bit 7 6 5 4 3 2 1 0
1511 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1513 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1514 (cycle_time_ns_x_100[cas_index] != 0)) {
1515 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1516 cycle_time_ns_x_100[cas_index]);
1521 cas_4_0_available = false;
1524 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1525 (cycle_time_ns_x_100[cas_index] != 0)) {
1526 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1527 cycle_time_ns_x_100[cas_index]);
1532 cas_3_0_available = false;
1535 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1536 (cycle_time_ns_x_100[cas_index] != 0)) {
1537 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1538 cycle_time_ns_x_100[cas_index]);
1543 cas_2_5_available = false;
1546 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1547 (cycle_time_ns_x_100[cas_index] != 0)) {
1548 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1549 cycle_time_ns_x_100[cas_index]);
1554 cas_2_0_available = false;
1558 * DDR2 devices use the following bitmask for CAS latency:
1559 * Bit 7 6 5 4 3 2 1 0
1560 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1562 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1563 (cycle_time_ns_x_100[cas_index] != 0)) {
1564 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1565 cycle_time_ns_x_100[cas_index]);
1570 cas_5_0_available = false;
1573 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1574 (cycle_time_ns_x_100[cas_index] != 0)) {
1575 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1576 cycle_time_ns_x_100[cas_index]);
1581 cas_4_0_available = false;
1584 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1585 (cycle_time_ns_x_100[cas_index] != 0)) {
1586 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1587 cycle_time_ns_x_100[cas_index]);
1592 cas_3_0_available = false;
1598 /*------------------------------------------------------------------
1599 * Set the SDRAM mode, SDRAM_MMODE
1600 *-----------------------------------------------------------------*/
1601 mfsdram(SDRAM_MMODE, mmode);
1602 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1604 /* add 10 here because of rounding problems */
1605 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1606 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1607 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1608 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1609 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1610 debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1611 debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1612 debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1614 if (sdram_ddr1 == true) { /* DDR1 */
1615 if ((cas_2_0_available == true) &&
1616 (sdram_freq <= cycle_2_0_clk)) {
1617 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1618 *selected_cas = DDR_CAS_2;
1619 } else if ((cas_2_5_available == true) &&
1620 (sdram_freq <= cycle_2_5_clk)) {
1621 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1622 *selected_cas = DDR_CAS_2_5;
1623 } else if ((cas_3_0_available == true) &&
1624 (sdram_freq <= cycle_3_0_clk)) {
1625 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1626 *selected_cas = DDR_CAS_3;
1628 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1629 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1630 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1631 spd_ddr_init_hang ();
1634 debug("cas_3_0_available=%d\n", cas_3_0_available);
1635 debug("cas_4_0_available=%d\n", cas_4_0_available);
1636 debug("cas_5_0_available=%d\n", cas_5_0_available);
1637 if ((cas_3_0_available == true) &&
1638 (sdram_freq <= cycle_3_0_clk)) {
1639 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1640 *selected_cas = DDR_CAS_3;
1641 } else if ((cas_4_0_available == true) &&
1642 (sdram_freq <= cycle_4_0_clk)) {
1643 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1644 *selected_cas = DDR_CAS_4;
1645 } else if ((cas_5_0_available == true) &&
1646 (sdram_freq <= cycle_5_0_clk)) {
1647 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1648 *selected_cas = DDR_CAS_5;
1650 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1651 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1652 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1653 printf("cas3=%d cas4=%d cas5=%d\n",
1654 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1655 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1656 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1657 spd_ddr_init_hang ();
1661 if (sdram_ddr1 == true)
1662 mmode |= SDRAM_MMODE_WR_DDR1;
1665 /* loop through all the DIMM slots on the board */
1666 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1667 /* If a dimm is installed in a particular slot ... */
1668 if (dimm_populated[dimm_num] != SDRAM_NONE)
1669 t_wr_ns = max(t_wr_ns,
1670 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1674 * convert from nanoseconds to ddr clocks
1675 * round up if necessary
1677 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1678 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1679 if (sdram_freq != ddr_check)
1687 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1690 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1693 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1696 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1699 *write_recovery = t_wr_clk;
1702 debug("CAS latency = %d\n", *selected_cas);
1703 debug("Write recovery = %d\n", *write_recovery);
1705 mtsdram(SDRAM_MMODE, mmode);
1708 /*-----------------------------------------------------------------------------+
1710 *-----------------------------------------------------------------------------*/
1711 static void program_rtr(unsigned long *dimm_populated,
1712 unsigned char *iic0_dimm_addr,
1713 unsigned long num_dimm_banks)
1715 PPC4xx_SYS_INFO board_cfg;
1716 unsigned long max_refresh_rate;
1717 unsigned long dimm_num;
1718 unsigned long refresh_rate_type;
1719 unsigned long refresh_rate;
1721 unsigned long sdram_freq;
1722 unsigned long sdr_ddrpll;
1725 /*------------------------------------------------------------------
1726 * Get the board configuration info.
1727 *-----------------------------------------------------------------*/
1728 get_sys_info(&board_cfg);
1730 /*------------------------------------------------------------------
1731 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1732 *-----------------------------------------------------------------*/
1733 mfsdr(SDR0_DDR0, sdr_ddrpll);
1734 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1736 max_refresh_rate = 0;
1737 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1738 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1740 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1741 refresh_rate_type &= 0x7F;
1742 switch (refresh_rate_type) {
1744 refresh_rate = 15625;
1747 refresh_rate = 3906;
1750 refresh_rate = 7812;
1753 refresh_rate = 31250;
1756 refresh_rate = 62500;
1759 refresh_rate = 125000;
1763 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1764 (unsigned int)dimm_num);
1765 printf("Replace the DIMM module with a supported DIMM.\n\n");
1766 spd_ddr_init_hang ();
1770 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1774 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1775 mfsdram(SDRAM_RTR, val);
1776 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1777 (SDRAM_RTR_RINT_ENCODE(rint)));
1780 /*------------------------------------------------------------------
1781 * This routine programs the SDRAM_TRx registers.
1782 *-----------------------------------------------------------------*/
1783 static void program_tr(unsigned long *dimm_populated,
1784 unsigned char *iic0_dimm_addr,
1785 unsigned long num_dimm_banks)
1787 unsigned long dimm_num;
1788 unsigned long sdram_ddr1;
1789 unsigned long t_rp_ns;
1790 unsigned long t_rcd_ns;
1791 unsigned long t_rrd_ns;
1792 unsigned long t_ras_ns;
1793 unsigned long t_rc_ns;
1794 unsigned long t_rfc_ns;
1795 unsigned long t_wpc_ns;
1796 unsigned long t_wtr_ns;
1797 unsigned long t_rpc_ns;
1798 unsigned long t_rp_clk;
1799 unsigned long t_rcd_clk;
1800 unsigned long t_rrd_clk;
1801 unsigned long t_ras_clk;
1802 unsigned long t_rc_clk;
1803 unsigned long t_rfc_clk;
1804 unsigned long t_wpc_clk;
1805 unsigned long t_wtr_clk;
1806 unsigned long t_rpc_clk;
1807 unsigned long sdtr1, sdtr2, sdtr3;
1808 unsigned long ddr_check;
1809 unsigned long sdram_freq;
1810 unsigned long sdr_ddrpll;
1812 PPC4xx_SYS_INFO board_cfg;
1814 /*------------------------------------------------------------------
1815 * Get the board configuration info.
1816 *-----------------------------------------------------------------*/
1817 get_sys_info(&board_cfg);
1819 mfsdr(SDR0_DDR0, sdr_ddrpll);
1820 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1822 /*------------------------------------------------------------------
1823 * Handle the timing. We need to find the worst case timing of all
1824 * the dimm modules installed.
1825 *-----------------------------------------------------------------*/
1837 /* loop through all the DIMM slots on the board */
1838 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1839 /* If a dimm is installed in a particular slot ... */
1840 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1841 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1846 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1847 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1848 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1849 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1850 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1851 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1855 /*------------------------------------------------------------------
1856 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1857 *-----------------------------------------------------------------*/
1858 mfsdram(SDRAM_SDTR1, sdtr1);
1859 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1860 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1862 /* default values */
1863 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1864 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1866 /* normal operations */
1867 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1868 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1870 mtsdram(SDRAM_SDTR1, sdtr1);
1872 /*------------------------------------------------------------------
1873 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1874 *-----------------------------------------------------------------*/
1875 mfsdram(SDRAM_SDTR2, sdtr2);
1876 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1877 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1878 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1879 SDRAM_SDTR2_RRD_MASK);
1882 * convert t_rcd from nanoseconds to ddr clocks
1883 * round up if necessary
1885 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1886 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1887 if (sdram_freq != ddr_check)
1890 switch (t_rcd_clk) {
1893 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1896 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1899 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1902 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1905 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1909 if (sdram_ddr1 == true) { /* DDR1 */
1910 if (sdram_freq < 200000000) {
1911 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1912 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1913 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1915 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1916 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1917 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1920 /* loop through all the DIMM slots on the board */
1921 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1922 /* If a dimm is installed in a particular slot ... */
1923 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1924 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1925 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1926 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1931 * convert from nanoseconds to ddr clocks
1932 * round up if necessary
1934 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1935 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1936 if (sdram_freq != ddr_check)
1939 switch (t_wpc_clk) {
1943 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1946 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1949 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1952 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1955 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1960 * convert from nanoseconds to ddr clocks
1961 * round up if necessary
1963 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1964 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1965 if (sdram_freq != ddr_check)
1968 switch (t_wtr_clk) {
1971 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1974 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1977 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1980 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1985 * convert from nanoseconds to ddr clocks
1986 * round up if necessary
1988 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1989 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1990 if (sdram_freq != ddr_check)
1993 switch (t_rpc_clk) {
1997 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2000 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2003 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2009 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2012 * convert t_rrd from nanoseconds to ddr clocks
2013 * round up if necessary
2015 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2016 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2017 if (sdram_freq != ddr_check)
2021 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2023 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2026 * convert t_rp from nanoseconds to ddr clocks
2027 * round up if necessary
2029 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2030 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2031 if (sdram_freq != ddr_check)
2039 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2042 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2045 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2048 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2051 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2055 mtsdram(SDRAM_SDTR2, sdtr2);
2057 /*------------------------------------------------------------------
2058 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2059 *-----------------------------------------------------------------*/
2060 mfsdram(SDRAM_SDTR3, sdtr3);
2061 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2062 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2065 * convert t_ras from nanoseconds to ddr clocks
2066 * round up if necessary
2068 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2069 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2070 if (sdram_freq != ddr_check)
2073 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2076 * convert t_rc from nanoseconds to ddr clocks
2077 * round up if necessary
2079 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2080 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2081 if (sdram_freq != ddr_check)
2084 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2086 /* default xcs value */
2087 sdtr3 |= SDRAM_SDTR3_XCS;
2090 * convert t_rfc from nanoseconds to ddr clocks
2091 * round up if necessary
2093 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2094 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2095 if (sdram_freq != ddr_check)
2098 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2100 mtsdram(SDRAM_SDTR3, sdtr3);
2103 /*-----------------------------------------------------------------------------+
2105 *-----------------------------------------------------------------------------*/
2106 static void program_bxcf(unsigned long *dimm_populated,
2107 unsigned char *iic0_dimm_addr,
2108 unsigned long num_dimm_banks)
2110 unsigned long dimm_num;
2111 unsigned long num_col_addr;
2112 unsigned long num_ranks;
2113 unsigned long num_banks;
2115 unsigned long ind_rank;
2117 unsigned long ind_bank;
2118 unsigned long bank_0_populated;
2120 /*------------------------------------------------------------------
2121 * Set the BxCF regs. First, wipe out the bank config registers.
2122 *-----------------------------------------------------------------*/
2123 mtsdram(SDRAM_MB0CF, 0x00000000);
2124 mtsdram(SDRAM_MB1CF, 0x00000000);
2125 mtsdram(SDRAM_MB2CF, 0x00000000);
2126 mtsdram(SDRAM_MB3CF, 0x00000000);
2128 mode = SDRAM_BXCF_M_BE_ENABLE;
2130 bank_0_populated = 0;
2132 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2133 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2134 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2135 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2136 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2137 num_ranks = (num_ranks & 0x0F) +1;
2139 num_ranks = num_ranks & 0x0F;
2141 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2143 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2148 switch (num_col_addr) {
2150 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2153 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2156 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2159 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2162 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2165 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2166 (unsigned int)dimm_num);
2167 printf("ERROR: Unsupported value for number of "
2168 "column addresses: %d.\n", (unsigned int)num_col_addr);
2169 printf("Replace the DIMM module with a supported DIMM.\n\n");
2170 spd_ddr_init_hang ();
2174 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2175 bank_0_populated = 1;
2177 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2178 mtsdram(SDRAM_MB0CF +
2179 ((dimm_num + bank_0_populated + ind_rank) << 2),
2186 /*------------------------------------------------------------------
2187 * program memory queue.
2188 *-----------------------------------------------------------------*/
2189 static void program_memory_queue(unsigned long *dimm_populated,
2190 unsigned char *iic0_dimm_addr,
2191 unsigned long num_dimm_banks)
2193 unsigned long dimm_num;
2194 phys_size_t rank_base_addr;
2195 unsigned long rank_reg;
2196 phys_size_t rank_size_bytes;
2197 unsigned long rank_size_id;
2198 unsigned long num_ranks;
2199 unsigned long baseadd_size;
2201 unsigned long bank_0_populated = 0;
2202 phys_size_t total_size = 0;
2204 /*------------------------------------------------------------------
2205 * Reset the rank_base_address.
2206 *-----------------------------------------------------------------*/
2207 rank_reg = SDRAM_R0BAS;
2209 rank_base_addr = 0x00000000;
2211 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2212 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2213 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2214 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2215 num_ranks = (num_ranks & 0x0F) + 1;
2217 num_ranks = num_ranks & 0x0F;
2219 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2221 /*------------------------------------------------------------------
2223 *-----------------------------------------------------------------*/
2225 switch (rank_size_id) {
2227 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2231 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2235 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2239 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2243 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2247 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2251 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2255 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2259 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2260 (unsigned int)dimm_num);
2261 printf("ERROR: Unsupported value for the banksize: %d.\n",
2262 (unsigned int)rank_size_id);
2263 printf("Replace the DIMM module with a supported DIMM.\n\n");
2264 spd_ddr_init_hang ();
2266 rank_size_bytes = total_size << 20;
2268 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2269 bank_0_populated = 1;
2271 for (i = 0; i < num_ranks; i++) {
2272 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2273 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2275 rank_base_addr += rank_size_bytes;
2280 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2281 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2282 defined(CONFIG_460SX)
2284 * Enable high bandwidth access
2285 * This is currently not used, but with this setup
2286 * it is possible to use it later on in e.g. the Linux
2287 * EMAC driver for performance gain.
2289 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2290 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2293 * Set optimal value for Memory Queue HB/LL Configuration registers
2295 mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2296 SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2297 SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2298 mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2299 SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2300 SDRAM_CONF1LL_RPLM);
2301 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2305 #ifdef CONFIG_DDR_ECC
2306 /*-----------------------------------------------------------------------------+
2308 *-----------------------------------------------------------------------------*/
2309 static void program_ecc(unsigned long *dimm_populated,
2310 unsigned char *iic0_dimm_addr,
2311 unsigned long num_dimm_banks,
2312 unsigned long tlb_word2_i_value)
2314 unsigned long dimm_num;
2318 /* loop through all the DIMM slots on the board */
2319 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2320 /* If a dimm is installed in a particular slot ... */
2321 if (dimm_populated[dimm_num] != SDRAM_NONE)
2322 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2327 do_program_ecc(tlb_word2_i_value);
2331 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2332 /*-----------------------------------------------------------------------------+
2333 * program_DQS_calibration.
2334 *-----------------------------------------------------------------------------*/
2335 static void program_DQS_calibration(unsigned long *dimm_populated,
2336 unsigned char *iic0_dimm_addr,
2337 unsigned long num_dimm_banks)
2341 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2342 mtsdram(SDRAM_RQDC, 0x80000037);
2343 mtsdram(SDRAM_RDCC, 0x40000000);
2344 mtsdram(SDRAM_RFDC, 0x000001DF);
2348 /*------------------------------------------------------------------
2349 * Program RDCC register
2350 * Read sample cycle auto-update enable
2351 *-----------------------------------------------------------------*/
2353 mfsdram(SDRAM_RDCC, val);
2355 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2356 | SDRAM_RDCC_RSAE_ENABLE);
2358 /*------------------------------------------------------------------
2359 * Program RQDC register
2360 * Internal DQS delay mechanism enable
2361 *-----------------------------------------------------------------*/
2362 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2364 /*------------------------------------------------------------------
2365 * Program RFDC register
2366 * Set Feedback Fractional Oversample
2367 * Auto-detect read sample cycle enable
2368 * Set RFOS to 1/4 of memclk cycle (0x3f)
2369 *-----------------------------------------------------------------*/
2370 mfsdram(SDRAM_RFDC, val);
2372 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2373 SDRAM_RFDC_RFFD_MASK))
2374 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2375 SDRAM_RFDC_RFFD_ENCODE(0)));
2377 DQS_calibration_process();
2381 static int short_mem_test(void)
2388 phys_size_t base_addr;
2389 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2390 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2391 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2392 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2393 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2394 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2395 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2396 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2397 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2398 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2399 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2400 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2401 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2402 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2403 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2404 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2405 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2408 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2409 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2412 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2413 /* Bank is enabled */
2416 * Only run test on accessable memory (below 2GB)
2418 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2419 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2422 /*------------------------------------------------------------------
2423 * Run the short memory test.
2424 *-----------------------------------------------------------------*/
2425 membase = (u32 *)(u32)base_addr;
2427 for (i = 0; i < NUMMEMTESTS; i++) {
2428 for (j = 0; j < NUMMEMWORDS; j++) {
2429 membase[j] = test[i][j];
2430 ppcDcbf((u32)&(membase[j]));
2433 for (l=0; l<NUMLOOPS; l++) {
2434 for (j = 0; j < NUMMEMWORDS; j++) {
2435 if (membase[j] != test[i][j]) {
2436 ppcDcbf((u32)&(membase[j]));
2439 ppcDcbf((u32)&(membase[j]));
2444 } /* if bank enabled */
2445 } /* for bxcf_num */
2450 #ifndef HARD_CODED_DQS
2451 /*-----------------------------------------------------------------------------+
2452 * DQS_calibration_process.
2453 *-----------------------------------------------------------------------------*/
2454 static void DQS_calibration_process(void)
2456 unsigned long rfdc_reg;
2461 unsigned long dlycal;
2462 unsigned long dly_val;
2463 unsigned long max_pass_length;
2464 unsigned long current_pass_length;
2465 unsigned long current_fail_length;
2466 unsigned long current_start;
2468 unsigned char fail_found;
2469 unsigned char pass_found;
2470 #if !defined(CONFIG_DDR_RQDC_FIXED)
2477 char str[] = "Auto calibration -";
2478 char slash[] = "\\|/-\\|/-";
2480 /*------------------------------------------------------------------
2481 * Test to determine the best read clock delay tuning bits.
2483 * Before the DDR controller can be used, the read clock delay needs to be
2484 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2485 * This value cannot be hardcoded into the program because it changes
2486 * depending on the board's setup and environment.
2487 * To do this, all delay values are tested to see if they
2488 * work or not. By doing this, you get groups of fails with groups of
2489 * passing values. The idea is to find the start and end of a passing
2490 * window and take the center of it to use as the read clock delay.
2492 * A failure has to be seen first so that when we hit a pass, we know
2493 * that it is truely the start of the window. If we get passing values
2494 * to start off with, we don't know if we are at the start of the window.
2496 * The code assumes that a failure will always be found.
2497 * If a failure is not found, there is no easy way to get the middle
2498 * of the passing window. I guess we can pretty much pick any value
2499 * but some values will be better than others. Since the lowest speed
2500 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2501 * from experimentation it is safe to say you will always have a failure.
2502 *-----------------------------------------------------------------*/
2504 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2505 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2510 mfsdram(SDRAM_RQDC, rqdc_reg);
2511 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2512 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2513 #else /* CONFIG_DDR_RQDC_FIXED */
2515 * On Katmai the complete auto-calibration somehow doesn't seem to
2516 * produce the best results, meaning optimal values for RQFD/RFFD.
2517 * This was discovered by GDA using a high bandwidth scope,
2518 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2519 * so now on Katmai "only" RFFD is auto-calibrated.
2521 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2522 #endif /* CONFIG_DDR_RQDC_FIXED */
2526 max_pass_length = 0;
2529 current_pass_length = 0;
2530 current_fail_length = 0;
2536 * get the delay line calibration register value
2538 mfsdram(SDRAM_DLCR, dlycal);
2539 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2541 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2542 mfsdram(SDRAM_RFDC, rfdc_reg);
2543 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2545 /*------------------------------------------------------------------
2546 * Set the timing reg for the test.
2547 *-----------------------------------------------------------------*/
2548 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2550 /*------------------------------------------------------------------
2551 * See if the rffd value passed.
2552 *-----------------------------------------------------------------*/
2553 if (short_mem_test()) {
2554 if (fail_found == true) {
2556 if (current_pass_length == 0)
2557 current_start = rffd;
2559 current_fail_length = 0;
2560 current_pass_length++;
2562 if (current_pass_length > max_pass_length) {
2563 max_pass_length = current_pass_length;
2564 max_start = current_start;
2569 current_pass_length = 0;
2570 current_fail_length++;
2572 if (current_fail_length >= (dly_val >> 2)) {
2573 if (fail_found == false)
2575 else if (pass_found == true)
2581 /*------------------------------------------------------------------
2582 * Set the average RFFD value
2583 *-----------------------------------------------------------------*/
2584 rffd_average = ((max_start + max_end) >> 1);
2586 if (rffd_average < 0)
2589 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2590 rffd_average = SDRAM_RFDC_RFFD_MAX;
2591 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2592 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2594 #if !defined(CONFIG_DDR_RQDC_FIXED)
2595 max_pass_length = 0;
2598 current_pass_length = 0;
2599 current_fail_length = 0;
2601 window_found = false;
2605 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2606 mfsdram(SDRAM_RQDC, rqdc_reg);
2607 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2609 /*------------------------------------------------------------------
2610 * Set the timing reg for the test.
2611 *-----------------------------------------------------------------*/
2612 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2614 /*------------------------------------------------------------------
2615 * See if the rffd value passed.
2616 *-----------------------------------------------------------------*/
2617 if (short_mem_test()) {
2618 if (fail_found == true) {
2620 if (current_pass_length == 0)
2621 current_start = rqfd;
2623 current_fail_length = 0;
2624 current_pass_length++;
2626 if (current_pass_length > max_pass_length) {
2627 max_pass_length = current_pass_length;
2628 max_start = current_start;
2633 current_pass_length = 0;
2634 current_fail_length++;
2636 if (fail_found == false) {
2638 } else if (pass_found == true) {
2639 window_found = true;
2645 rqfd_average = ((max_start + max_end) >> 1);
2647 /*------------------------------------------------------------------
2648 * Make sure we found the valid read passing window. Halt if not
2649 *-----------------------------------------------------------------*/
2650 if (window_found == false) {
2651 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2653 putc(slash[loopi++ % 8]);
2655 /* try again from with a different RQFD start value */
2657 goto calibration_loop;
2660 printf("\nERROR: Cannot determine a common read delay for the "
2661 "DIMM(s) installed.\n");
2662 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2663 ppc4xx_ibm_ddr2_register_dump();
2664 spd_ddr_init_hang ();
2667 if (rqfd_average < 0)
2670 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2671 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2674 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2675 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2677 blank_string(strlen(str));
2678 #endif /* CONFIG_DDR_RQDC_FIXED */
2680 mfsdram(SDRAM_DLCR, val);
2681 debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2682 mfsdram(SDRAM_RQDC, val);
2683 debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2684 mfsdram(SDRAM_RFDC, val);
2685 debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2686 mfsdram(SDRAM_RDCC, val);
2687 debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2689 #else /* calibration test with hardvalues */
2690 /*-----------------------------------------------------------------------------+
2691 * DQS_calibration_process.
2692 *-----------------------------------------------------------------------------*/
2693 static void test(void)
2695 unsigned long dimm_num;
2696 unsigned long ecc_temp;
2698 unsigned long *membase;
2699 unsigned long bxcf[MAXRANKS];
2702 char begin_found[MAXDIMMS];
2703 char end_found[MAXDIMMS];
2704 char search_end[MAXDIMMS];
2705 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2706 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2707 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2708 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2709 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2710 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2711 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2712 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2713 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2714 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2715 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2716 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2717 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2718 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2719 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2720 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2721 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2723 /*------------------------------------------------------------------
2724 * Test to determine the best read clock delay tuning bits.
2726 * Before the DDR controller can be used, the read clock delay needs to be
2727 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2728 * This value cannot be hardcoded into the program because it changes
2729 * depending on the board's setup and environment.
2730 * To do this, all delay values are tested to see if they
2731 * work or not. By doing this, you get groups of fails with groups of
2732 * passing values. The idea is to find the start and end of a passing
2733 * window and take the center of it to use as the read clock delay.
2735 * A failure has to be seen first so that when we hit a pass, we know
2736 * that it is truely the start of the window. If we get passing values
2737 * to start off with, we don't know if we are at the start of the window.
2739 * The code assumes that a failure will always be found.
2740 * If a failure is not found, there is no easy way to get the middle
2741 * of the passing window. I guess we can pretty much pick any value
2742 * but some values will be better than others. Since the lowest speed
2743 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2744 * from experimentation it is safe to say you will always have a failure.
2745 *-----------------------------------------------------------------*/
2746 mfsdram(SDRAM_MCOPT1, ecc_temp);
2747 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2748 mfsdram(SDRAM_MCOPT1, val);
2749 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2750 SDRAM_MCOPT1_MCHK_NON);
2752 window_found = false;
2753 begin_found[0] = false;
2754 end_found[0] = false;
2755 search_end[0] = false;
2756 begin_found[1] = false;
2757 end_found[1] = false;
2758 search_end[1] = false;
2760 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2761 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2764 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2766 /* Bank is enabled */
2768 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2770 /*------------------------------------------------------------------
2771 * Run the short memory test.
2772 *-----------------------------------------------------------------*/
2773 for (i = 0; i < NUMMEMTESTS; i++) {
2774 for (j = 0; j < NUMMEMWORDS; j++) {
2775 membase[j] = test[i][j];
2776 ppcDcbf((u32)&(membase[j]));
2779 for (j = 0; j < NUMMEMWORDS; j++) {
2780 if (membase[j] != test[i][j]) {
2781 ppcDcbf((u32)&(membase[j]));
2784 ppcDcbf((u32)&(membase[j]));
2787 if (j < NUMMEMWORDS)
2791 /*------------------------------------------------------------------
2792 * See if the rffd value passed.
2793 *-----------------------------------------------------------------*/
2794 if (i < NUMMEMTESTS) {
2795 if ((end_found[dimm_num] == false) &&
2796 (search_end[dimm_num] == true)) {
2797 end_found[dimm_num] = true;
2799 if ((end_found[0] == true) &&
2800 (end_found[1] == true))
2803 if (begin_found[dimm_num] == false) {
2804 begin_found[dimm_num] = true;
2805 search_end[dimm_num] = true;
2809 begin_found[dimm_num] = true;
2810 end_found[dimm_num] = true;
2814 if ((begin_found[0] == true) && (begin_found[1] == true))
2815 window_found = true;
2817 /*------------------------------------------------------------------
2818 * Make sure we found the valid read passing window. Halt if not
2819 *-----------------------------------------------------------------*/
2820 if (window_found == false) {
2821 printf("ERROR: Cannot determine a common read delay for the "
2822 "DIMM(s) installed.\n");
2823 spd_ddr_init_hang ();
2826 /*------------------------------------------------------------------
2827 * Restore the ECC variable to what it originally was
2828 *-----------------------------------------------------------------*/
2829 mtsdram(SDRAM_MCOPT1,
2830 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2833 #endif /* !HARD_CODED_DQS */
2834 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2836 #else /* CONFIG_SPD_EEPROM */
2838 /*-----------------------------------------------------------------------------
2839 * Function: initdram
2840 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2841 * The configuration is performed using static, compile-
2843 * Configures the PPC405EX(r) and PPC460EX/GT
2844 *---------------------------------------------------------------------------*/
2845 phys_size_t initdram(int board_type)
2848 * Only run this SDRAM init code once. For NAND booting
2849 * targets like Kilauea, we call initdram() early from the
2850 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2851 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2852 * which calls initdram() again. This time the controller
2853 * mustn't be reconfigured again since we're already running
2856 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2859 #if defined(CONFIG_440)
2860 mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
2861 mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
2862 mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
2863 mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
2864 mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
2865 mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
2866 mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
2867 mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
2868 mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
2871 /* Set Memory Bank Configuration Registers */
2873 mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2874 mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2875 mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2876 mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2878 /* Set Memory Clock Timing Register */
2880 mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
2882 /* Set Refresh Time Register */
2884 mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
2886 /* Set SDRAM Timing Registers */
2888 mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2889 mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2890 mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
2892 /* Set Mode and Extended Mode Registers */
2894 mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2895 mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
2897 /* Set Memory Controller Options 1 Register */
2899 mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
2901 /* Set Manual Initialization Control Registers */
2903 mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2904 mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2905 mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2906 mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2907 mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2908 mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2909 mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2910 mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2911 mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2912 mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2913 mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2914 mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2915 mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2916 mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2917 mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2918 mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
2920 /* Set On-Die Termination Registers */
2922 mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2923 mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2924 mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
2926 /* Set Write Timing Register */
2928 mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
2931 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2932 * SDRAM0_MCOPT2[IPTR] = 1
2935 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2936 SDRAM_MCOPT2_IPTR_EXECUTE));
2939 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2940 * completion of initialization.
2944 mfsdram(SDRAM_MCSTAT, val);
2945 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2947 /* Set Delay Control Registers */
2949 mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
2951 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2952 mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2953 mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2954 mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
2955 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2958 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
2961 mfsdram(SDRAM_MCOPT2, val);
2962 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
2964 #if defined(CONFIG_440)
2966 * Program TLB entries with caches enabled, for best performace
2967 * while auto-calibrating and ECC generation
2969 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
2972 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2973 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
2974 /*------------------------------------------------------------------
2976 +-----------------------------------------------------------------*/
2977 DQS_autocalibration();
2978 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
2979 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2982 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2983 * PowerPC440SP/SPe DDR2 application note:
2984 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2988 #if defined(CONFIG_DDR_ECC)
2990 #endif /* defined(CONFIG_DDR_ECC) */
2992 #if defined(CONFIG_440)
2994 * Now after initialization (auto-calibration and ECC generation)
2995 * remove the TLB entries with caches enabled and program again with
2996 * desired cache functionality
2998 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
2999 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3002 ppc4xx_ibm_ddr2_register_dump();
3004 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3006 * Clear potential errors resulting from auto-calibration.
3007 * If not done, then we could get an interrupt later on when
3008 * exceptions are enabled.
3010 set_mcsr(get_mcsr());
3011 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3013 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3015 return (CONFIG_SYS_MBYTES_SDRAM << 20);
3017 #endif /* CONFIG_SPD_EEPROM */
3019 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3020 #if defined(CONFIG_440)
3021 u32 mfdcr_any(u32 dcr)
3026 case SDRAM_R0BAS + 0:
3027 val = mfdcr(SDRAM_R0BAS + 0);
3029 case SDRAM_R0BAS + 1:
3030 val = mfdcr(SDRAM_R0BAS + 1);
3032 case SDRAM_R0BAS + 2:
3033 val = mfdcr(SDRAM_R0BAS + 2);
3035 case SDRAM_R0BAS + 3:
3036 val = mfdcr(SDRAM_R0BAS + 3);
3039 printf("DCR %d not defined in case statement!!!\n", dcr);
3040 val = 0; /* just to satisfy the compiler */
3046 void mtdcr_any(u32 dcr, u32 val)
3049 case SDRAM_R0BAS + 0:
3050 mtdcr(SDRAM_R0BAS + 0, val);
3052 case SDRAM_R0BAS + 1:
3053 mtdcr(SDRAM_R0BAS + 1, val);
3055 case SDRAM_R0BAS + 2:
3056 mtdcr(SDRAM_R0BAS + 2, val);
3058 case SDRAM_R0BAS + 3:
3059 mtdcr(SDRAM_R0BAS + 3, val);
3062 printf("DCR %d not defined in case statement!!!\n", dcr);
3065 #endif /* defined(CONFIG_440) */
3066 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3068 inline void ppc4xx_ibm_ddr2_register_dump(void)
3071 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3073 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3074 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3075 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3076 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3077 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3078 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3079 #endif /* (defined(CONFIG_440SP) || ... */
3080 #if defined(CONFIG_405EX)
3081 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3082 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3083 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3084 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3085 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3086 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3087 #endif /* defined(CONFIG_405EX) */
3088 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3089 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3090 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3091 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3092 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3093 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3094 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3095 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3096 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3097 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3098 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3099 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3100 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3101 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3102 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3103 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3105 * OPART is only used as a trigger register.
3107 * No data is contained in this register, and reading or writing
3108 * to is can cause bad things to happen (hangs). Just skip it and
3111 printf("%20s = N/A\n", "SDRAM_OPART");
3112 #endif /* defined(CONFIG_440SP) || ... */
3113 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3114 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3115 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3116 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3117 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3118 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3119 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3120 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3121 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3122 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3123 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3124 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3125 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3126 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3127 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3128 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3129 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3130 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3131 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3132 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3133 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3134 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3140 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3141 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
3142 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3143 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3144 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3145 #endif /* defined(CONFIG_440SP) || ... */
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3147 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3148 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3149 #endif /* defined(DEBUG) */