2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/fsl_law.h>
23 #include <asm/fsl_serdes.h>
24 #include <asm/fsl_srio.h>
25 #include <asm/errno.h>
27 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
28 #define SRIO_PORT_ACCEPT_ALL 0x10000001
29 #define SRIO_IB_ATMU_AR 0x80f55000
30 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
31 #define SRIO_OB_ATMU_AR_RW 0x80045000
32 #define SRIO_LCSBA1CSR_OFFSET 0x5c
33 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
34 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
35 #define SRIO_LCSBA1CSR 0x60000000
38 #if defined(CONFIG_FSL_CORENET)
39 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
40 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
41 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
43 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
44 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
46 #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
47 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
48 #elif defined(CONFIG_MPC85xx)
49 #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
50 #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
51 #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
52 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
53 #elif defined(CONFIG_MPC86xx)
54 #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
55 #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
56 #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
57 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
58 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
60 #error "No defines for DEVDISR_SRIO"
63 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
67 * Description: During port initialization, the SRIO port performs
68 * lane synchronization (detecting valid symbols on a lane) and
69 * lane alignment (coordinating multiple lanes to receive valid data
70 * across lanes). Internal errors in lane synchronization and lane
71 * alignment may cause failure to achieve link initialization at
72 * the configured port width.
73 * An SRIO port configured as a 4x port may see one of these scenarios:
74 * 1. One or more lanes fails to achieve lane synchronization. Depending
75 * on which lanes fail, this may result in downtraining from 4x to 1x
76 * on lane 0, 4x to 1x on lane R (redundant lane).
77 * 2. The link may fail to achieve lane alignment as a 4x, even though
78 * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
79 * An SRIO port configured as a 1x port may fail to complete port
80 * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
81 * Impact: SRIO port may downtrain to 1x, or may fail to complete
82 * link initialization. Once a port completes link initialization
83 * successfully, it will operate normally.
85 static int srio_erratum_a004034(u8 port)
87 serdes_corenet_t *srds_regs;
92 unsigned long long end_tick;
93 struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
95 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
96 conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
97 >> (12 - port * 4)) & 0x3;
98 init_lane = (in_be32((void *)&srio_regs->lp_serial
99 .port[port].pccsr) >> 27) & 0x7;
102 * Start a counter set to ~2 ms after the SERDES reset is
103 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
104 * corresponding to the SERDES bank/PLL for the SRIO port).
106 if (in_be32((void *)&srds_regs->bank[0].rstctl)
107 & SRDS_RSTCTL_RSTDONE) {
109 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
110 * PO=1 or the counter expires. If the counter expires, the
111 * port has failed initialization: go to recover steps. If PO=1
112 * and the desired port width is 1x, go to normal steps. If
113 * PO = 1 and the desired port width is 4x, go to recover steps.
115 end_tick = usec2ticks(2000) + get_ticks();
117 if (in_be32((void *)&srio_regs->lp_serial
118 .port[port].pescsr) & 0x2) {
119 if (conf_lane == 0x1)
122 if (init_lane == 0x2)
128 } while (end_tick > get_ticks());
130 /* recover at most 3 times */
131 for (i = 0; i < 3; i++) {
132 /* Set SRIO PnCCSR[PD]=1 */
133 setbits_be32((void *)&srio_regs->lp_serial
137 * Set SRIO PnPCR[OBDEN] on the host to
138 * enable the discarding of any pending packets.
140 setbits_be32((void *)&srio_regs->impl.port[port].pcr,
144 /* Run sync command */
148 first = serdes_get_first_lane(SRIO2);
150 first = serdes_get_first_lane(SRIO1);
151 if (unlikely(first < 0))
153 if (conf_lane == 0x1)
158 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
161 for (idx = first; idx <= last; idx++)
162 clrbits_be32(&srds_regs->lane[idx].gcr0,
165 * Read SERDES BnGCRm0 for each SRIO
168 for (idx = first; idx <= last; idx++)
169 in_be32(&srds_regs->lane[idx].gcr0);
170 /* Run sync command */
175 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
178 for (idx = first; idx <= last; idx++)
179 setbits_be32(&srds_regs->lane[idx].gcr0,
182 * Read SERDES BnGCRm0 for each SRIO
185 for (idx = first; idx <= last; idx++)
186 in_be32(&srds_regs->lane[idx].gcr0);
187 /* Run sync command */
192 /* Write 1 to clear all bits in SRIO PnSLCSR */
193 out_be32((void *)&srio_regs->impl.port[port].slcsr,
195 /* Clear SRIO PnPCR[OBDEN] on the host */
196 clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
198 /* Set SRIO PnCCSR[PD]=0 */
199 clrbits_be32((void *)&srio_regs->lp_serial
204 /* Poll the state of the port again */
206 (in_be32((void *)&srio_regs->lp_serial
207 .port[port].pccsr) >> 27) & 0x7;
208 if (in_be32((void *)&srio_regs->lp_serial
209 .port[port].pescsr) & 0x2) {
210 if (conf_lane == 0x1)
213 if (init_lane == 0x2)
224 /* Poll PnESCSR[OES] on the host until it is clear */
225 end_tick = usec2ticks(1000000) + get_ticks();
227 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
229 out_be32(((void *)&srio_regs->lp_serial
230 .port[port].pescsr), 0xffffffff);
231 out_be32(((void *)&srio_regs->phys_err
232 .port[port].edcsr), 0);
233 out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
236 } while (end_tick > get_ticks());
244 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
245 int srio1_used = 0, srio2_used = 0;
248 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
249 devdisr = &gur->devdisr3;
251 devdisr = &gur->devdisr;
253 if (is_serdes_configured(SRIO1)) {
254 set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
255 law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
258 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
259 if (srio_erratum_a004034(0) < 0)
260 printf("SRIO1: enabled but port error\n");
263 printf("SRIO1: enabled\n");
265 printf("SRIO1: disabled\n");
269 if (is_serdes_configured(SRIO2)) {
270 set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
271 law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
274 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
275 if (srio_erratum_a004034(1) < 0)
276 printf("SRIO2: enabled but port error\n");
279 printf("SRIO2: enabled\n");
282 printf("SRIO2: disabled\n");
286 #ifdef CONFIG_FSL_CORENET
287 /* On FSL_CORENET devices we can disable individual ports */
289 setbits_be32(devdisr, _DEVDISR_SRIO1);
291 setbits_be32(devdisr, _DEVDISR_SRIO2);
294 /* neither port is used - disable everything */
295 if (!srio1_used && !srio2_used) {
296 setbits_be32(devdisr, _DEVDISR_SRIO1);
297 setbits_be32(devdisr, _DEVDISR_SRIO2);
298 setbits_be32(devdisr, _DEVDISR_RMU);
302 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
303 void srio_boot_master(int port)
305 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
307 /* set port accept-all */
308 out_be32((void *)&srio->impl.port[port - 1].ptaacr,
309 SRIO_PORT_ACCEPT_ALL);
311 debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
312 /* configure inbound window for slave's u-boot image */
313 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
314 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
315 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
316 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
317 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
318 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
319 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
320 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
321 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
322 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
324 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
326 /* configure inbound window for slave's u-boot image */
327 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
328 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
329 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
330 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
331 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
332 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
333 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
334 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
335 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
336 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
338 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
340 /* configure inbound window for slave's ucode and ENV */
341 debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
342 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
343 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
344 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
345 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
346 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
347 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
348 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
349 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
350 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
352 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
355 void srio_boot_master_release_slave(int port)
357 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
359 debug("SRIOBOOT - MASTER: "
360 "Check the port status and release slave core ...\n");
362 escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
364 if (escsr & 0x10100) {
365 debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
368 debug("SRIOBOOT - MASTER: "
369 "Port [ %d ] is ready, now release slave's core ...\n",
372 * configure outbound window
373 * with maintenance attribute to set slave's LCSBA1CSR
375 out_be32((void *)&srio->atmu.port[port - 1]
376 .outbw[1].rowtar, 0);
377 out_be32((void *)&srio->atmu.port[port - 1]
378 .outbw[1].rowtear, 0);
380 out_be32((void *)&srio->atmu.port[port - 1]
382 CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
384 out_be32((void *)&srio->atmu.port[port - 1]
386 CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
387 out_be32((void *)&srio->atmu.port[port - 1]
389 SRIO_OB_ATMU_AR_MAINT
390 | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
393 * configure outbound window
394 * with R/W attribute to set slave's BRR
396 out_be32((void *)&srio->atmu.port[port - 1]
398 SRIO_LCSBA1CSR >> 9);
399 out_be32((void *)&srio->atmu.port[port - 1]
400 .outbw[2].rowtear, 0);
402 out_be32((void *)&srio->atmu.port[port - 1]
404 (CONFIG_SYS_SRIO2_MEM_PHYS
405 + SRIO_MAINT_WIN_SIZE) >> 12);
407 out_be32((void *)&srio->atmu.port[port - 1]
409 (CONFIG_SYS_SRIO1_MEM_PHYS
410 + SRIO_MAINT_WIN_SIZE) >> 12);
411 out_be32((void *)&srio->atmu.port[port - 1]
414 | atmu_size_mask(SRIO_RW_WIN_SIZE));
417 * Set the LCSBA1CSR register in slave
418 * by the maint-outbound window
421 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
422 + SRIO_LCSBA1CSR_OFFSET,
424 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
425 + SRIO_LCSBA1CSR_OFFSET)
429 * And then set the BRR register
430 * to release slave core
432 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
433 + SRIO_MAINT_WIN_SIZE
434 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
435 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
437 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
438 + SRIO_LCSBA1CSR_OFFSET,
440 while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
441 + SRIO_LCSBA1CSR_OFFSET)
445 * And then set the BRR register
446 * to release slave core
448 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
449 + SRIO_MAINT_WIN_SIZE
450 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
451 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
453 debug("SRIOBOOT - MASTER: "
454 "Release slave successfully! Now the slave should start up!\n");
457 debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);