2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
8 #include <asm/fsl_lbc.h>
11 /* Boards should provide their own version of this if they use lbc sdram */
12 static void __lbc_sdram_init(void)
16 void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init")));
20 void print_lbc_regs(void)
24 printf("\nLocal Bus Controller Registers\n");
25 for (i = 0; i < 8; i++) {
26 printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
27 i, get_lbc_br(i), i, get_lbc_or(i));
29 printf("LBCR\t0x%08X\tLCRR\t0x%08X\n",
30 get_lbc_lbcr(), get_lbc_lcrr());
33 void init_early_memctl_regs(void)
37 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
38 /* Set the local bus monitor timeout value to the maximum */
39 clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
43 /* if cs1 is already set via debugger, leave cs0/cs1 alone */
44 if (get_lbc_br(1) & BR_V)
49 * Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
50 * preliminary addresses - these have to be modified later
51 * when FLASH size has been determined
53 #if defined(CONFIG_SYS_OR0_REMAP)
54 set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
56 #if defined(CONFIG_SYS_OR1_REMAP)
57 set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
59 /* now restrict to preliminary range */
61 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
62 set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
63 set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
66 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
67 set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
68 set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
72 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
73 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
74 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
77 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
78 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
79 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
82 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
83 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
84 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
87 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
88 set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
89 set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
92 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
93 set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
94 set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
97 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
98 set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
99 set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
104 * Configures a UPM. The function requires the respective MxMR to be set
105 * before calling this function. "size" is the number or entries, not a sizeof.
107 void upmconfig(uint upm, uint *table, uint size)
109 fsl_lbc_t *lbc = LBC_BASE_ADDR;
110 int i, mad, old_mad = 0;
111 u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
112 u32 msel = BR_UPMx_TO_MSEL(upm);
113 u32 *mxmr = &lbc->mamr + upm;
114 volatile u8 *dummy = NULL;
116 if (upm < UPMA || upm > UPMC) {
117 printf("Error: %s() Bad UPM index %d\n", __func__, upm);
122 * Find the address for the dummy write - scan all of the BRs until we
123 * find one matching the UPM and extract the base address bits from it.
125 for (i = 0; i < 8; i++) {
126 if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | msel)) {
127 dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
133 printf("Error: %s() No matching BR\n", __func__);
137 /* Program UPM using steps outlined by the reference manual */
138 for (i = 0; i < size; i++) {
139 out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
140 out_be32(&lbc->mdr, table[i]);
141 (void)in_be32(&lbc->mdr);
144 mad = in_be32(mxmr) & MxMR_MAD_MSK;
145 } while (mad <= old_mad && !(!mad && i == (size-1)));
149 /* Return to normal operation */
150 out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_NORM);