2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * calculate the organization and timing parameter
6 * from ddr3 spd, please refer to the spec
7 * JEDEC standard No.21-C 4_01_02_11R18.pdf
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * Version 2 as published by the Free Software Foundation.
15 #include <asm/fsl_ddr_sdram.h>
20 * Calculate the Density of each Physical Rank.
21 * Returned size is in bytes.
24 * sdram capacity(bit) / 8 * primary bus width / sdram width
26 * where: sdram capacity = spd byte4[3:0]
27 * primary bus width = spd byte8[2:0]
28 * sdram width = spd byte7[2:0]
30 * SPD byte4 - sdram density and banks
31 * bit[3:0] size(bit) size(byte)
40 * SPD byte8 - module memory bus width
41 * bit[2:0] primary bus width
47 * SPD byte7 - module organiztion
48 * bit[2:0] sdram device width
55 static unsigned long long
56 compute_ranksize(const ddr3_spd_eeprom_t *spd)
58 unsigned long long bsize;
60 int nbit_sdram_cap_bsize = 0;
61 int nbit_primary_bus_width = 0;
62 int nbit_sdram_width = 0;
64 if ((spd->density_banks & 0xf) < 7)
65 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
66 if ((spd->bus_width & 0x7) < 4)
67 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
68 if ((spd->organization & 0x7) < 4)
69 nbit_sdram_width = (spd->organization & 0x7) + 2;
71 bsize = 1ULL << (nbit_sdram_cap_bsize - 3
72 + nbit_primary_bus_width - nbit_sdram_width);
74 debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
80 * ddr_compute_dimm_parameters for DDR3 SPD
82 * Compute DIMM parameters based upon the SPD information in spd.
83 * Writes the results to the dimm_params_t structure pointed by pdimm.
87 ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
89 unsigned int dimm_number)
96 if (spd->mem_type != SPD_MEMTYPE_DDR3) {
97 printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
101 memset(pdimm, 0, sizeof(dimm_params_t));
105 retval = ddr3_spd_check(spd);
107 printf("DIMM %u: failed checksum\n", dimm_number);
112 * The part name in ASCII in the SPD EEPROM is not null terminated.
113 * Guarantee null termination here by presetting all bytes to 0
114 * and copying the part name in ASCII from the SPD onto it
116 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
117 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
119 /* DIMM organization parameters */
120 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
121 pdimm->rank_density = compute_ranksize(spd);
122 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
123 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
124 if ((spd->bus_width >> 3) & 0x3)
125 pdimm->ec_sdram_width = 8;
127 pdimm->ec_sdram_width = 0;
128 pdimm->data_width = pdimm->primary_sdram_width
129 + pdimm->ec_sdram_width;
131 /* These are the types defined by the JEDEC DDR3 SPD spec */
132 pdimm->mirrored_dimm = 0;
133 pdimm->registered_dimm = 0;
134 switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
135 case DDR3_SPD_MODULETYPE_RDIMM:
136 case DDR3_SPD_MODULETYPE_MINI_RDIMM:
137 /* Registered/buffered DIMMs */
138 pdimm->registered_dimm = 1;
139 for (i = 0; i < 16; i += 2) {
140 u8 rcw = spd->mod_section.registered.rcw[i/2];
141 pdimm->rcw[i] = (rcw >> 0) & 0x0F;
142 pdimm->rcw[i+1] = (rcw >> 4) & 0x0F;
146 case DDR3_SPD_MODULETYPE_UDIMM:
147 case DDR3_SPD_MODULETYPE_SO_DIMM:
148 case DDR3_SPD_MODULETYPE_MICRO_DIMM:
149 case DDR3_SPD_MODULETYPE_MINI_UDIMM:
150 /* Unbuffered DIMMs */
151 if (spd->mod_section.unbuffered.addr_mapping & 0x1)
152 pdimm->mirrored_dimm = 1;
156 printf("unknown module_type 0x%02X\n", spd->module_type);
160 /* SDRAM device parameters */
161 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
162 pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
163 pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
166 * The SPD spec has not the ECC bit,
167 * We consider the DIMM as ECC capability
168 * when the extension bus exist
170 if (pdimm->ec_sdram_width)
171 pdimm->edc_config = 0x02;
173 pdimm->edc_config = 0x00;
176 * The SPD spec has not the burst length byte
177 * but DDR3 spec has nature BL8 and BC4,
178 * BL8 -bit3, BC4 -bit2
180 pdimm->burst_lengths_bitmask = 0x0c;
181 pdimm->row_density = __ilog2(pdimm->rank_density);
183 /* MTB - medium timebase
184 * The unit in the SPD spec is ns,
185 * We convert it to ps.
186 * eg: MTB = 0.125ns (125ps)
188 mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
189 pdimm->mtb_ps = mtb_ps;
192 * sdram minimum cycle time
193 * we assume the MTB is 0.125ns
195 * tCK_min=15 MTB (1.875ns) ->DDR3-1066
196 * =12 MTB (1.5ns) ->DDR3-1333
197 * =10 MTB (1.25ns) ->DDR3-1600
199 pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps;
202 * CAS latency supported
207 pdimm->caslat_X = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
210 * min CAS latency time
212 * DDR3-800D 100 MTB (12.5ns)
213 * DDR3-1066F 105 MTB (13.125ns)
214 * DDR3-1333H 108 MTB (13.5ns)
215 * DDR3-1600H 90 MTB (11.25ns)
217 pdimm->tAA_ps = spd->tAA_min * mtb_ps;
220 * min write recovery time
222 * tWR_min = 120 MTB (15ns) -> all speed grades.
224 pdimm->tWR_ps = spd->tWR_min * mtb_ps;
227 * min RAS to CAS delay time
229 * DDR3-800 100 MTB (12.5ns)
230 * DDR3-1066F 105 MTB (13.125ns)
231 * DDR3-1333H 108 MTB (13.5ns)
232 * DDR3-1600H 90 MTB (11.25)
234 pdimm->tRCD_ps = spd->tRCD_min * mtb_ps;
237 * min row active to row active delay time
239 * DDR3-800(1KB page) 80 MTB (10ns)
240 * DDR3-1333(1KB page) 48 MTB (6ns)
242 pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
245 * min row precharge delay time
247 * DDR3-800D 100 MTB (12.5ns)
248 * DDR3-1066F 105 MTB (13.125ns)
249 * DDR3-1333H 108 MTB (13.5ns)
250 * DDR3-1600H 90 MTB (11.25ns)
252 pdimm->tRP_ps = spd->tRP_min * mtb_ps;
254 /* min active to precharge delay time
256 * DDR3-800D 300 MTB (37.5ns)
257 * DDR3-1066F 300 MTB (37.5ns)
258 * DDR3-1333H 288 MTB (36ns)
259 * DDR3-1600H 280 MTB (35ns)
261 pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
264 * min active to actice/refresh delay time
266 * DDR3-800D 400 MTB (50ns)
267 * DDR3-1066F 405 MTB (50.625ns)
268 * DDR3-1333H 396 MTB (49.5ns)
269 * DDR3-1600H 370 MTB (46.25ns)
271 pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
274 * min refresh recovery delay time
276 * 512Mb 720 MTB (90ns)
277 * 1Gb 880 MTB (110ns)
278 * 2Gb 1280 MTB (160ns)
280 pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
283 * min internal write to read command delay time
284 * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
285 * tWRT is at least 4 mclk independent of operating freq.
287 pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
290 * min internal read to precharge command delay time
291 * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
292 * tRTP is at least 4 mclk independent of operating freq.
294 pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
297 * Average periodic refresh interval
298 * tREFI = 7.8 us at normal temperature range
299 * = 3.9 us at ext temperature range
301 pdimm->refresh_rate_ps = 7800000;
304 * min four active window delay time
306 * DDR3-800(1KB page) 320 MTB (40ns)
307 * DDR3-1066(1KB page) 300 MTB (37.5ns)
308 * DDR3-1333(1KB page) 240 MTB (30ns)
309 * DDR3-1600(1KB page) 240 MTB (30ns)
311 pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)