2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
5 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
6 * cpu specific common code for 85xx/86xx processors.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/cache.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 struct cpu_type cpu_type_list [] = {
38 #if defined(CONFIG_MPC85xx)
39 CPU_TYPE_ENTRY(8533, 8533, 1),
40 CPU_TYPE_ENTRY(8535, 8535, 1),
41 CPU_TYPE_ENTRY(8536, 8536, 1),
42 CPU_TYPE_ENTRY(8540, 8540, 1),
43 CPU_TYPE_ENTRY(8541, 8541, 1),
44 CPU_TYPE_ENTRY(8543, 8543, 1),
45 CPU_TYPE_ENTRY(8544, 8544, 1),
46 CPU_TYPE_ENTRY(8545, 8545, 1),
47 CPU_TYPE_ENTRY(8547, 8547, 1),
48 CPU_TYPE_ENTRY(8548, 8548, 1),
49 CPU_TYPE_ENTRY(8555, 8555, 1),
50 CPU_TYPE_ENTRY(8560, 8560, 1),
51 CPU_TYPE_ENTRY(8567, 8567, 1),
52 CPU_TYPE_ENTRY(8568, 8568, 1),
53 CPU_TYPE_ENTRY(8569, 8569, 1),
54 CPU_TYPE_ENTRY(8572, 8572, 2),
55 CPU_TYPE_ENTRY(P1010, P1010, 1),
56 CPU_TYPE_ENTRY(P1011, P1011, 1),
57 CPU_TYPE_ENTRY(P1012, P1012, 1),
58 CPU_TYPE_ENTRY(P1013, P1013, 1),
59 CPU_TYPE_ENTRY(P1014, P1014, 1),
60 CPU_TYPE_ENTRY(P1017, P1017, 1),
61 CPU_TYPE_ENTRY(P1020, P1020, 2),
62 CPU_TYPE_ENTRY(P1021, P1021, 2),
63 CPU_TYPE_ENTRY(P1022, P1022, 2),
64 CPU_TYPE_ENTRY(P1023, P1023, 2),
65 CPU_TYPE_ENTRY(P1024, P1024, 2),
66 CPU_TYPE_ENTRY(P1025, P1025, 2),
67 CPU_TYPE_ENTRY(P2010, P2010, 1),
68 CPU_TYPE_ENTRY(P2020, P2020, 2),
69 CPU_TYPE_ENTRY(P2040, P2040, 4),
70 CPU_TYPE_ENTRY(P2041, P2041, 4),
71 CPU_TYPE_ENTRY(P3041, P3041, 4),
72 CPU_TYPE_ENTRY(P4040, P4040, 4),
73 CPU_TYPE_ENTRY(P4080, P4080, 8),
74 CPU_TYPE_ENTRY(P5010, P5010, 1),
75 CPU_TYPE_ENTRY(P5020, P5020, 2),
76 CPU_TYPE_ENTRY(P5021, P5021, 2),
77 CPU_TYPE_ENTRY(P5040, P5040, 4),
78 CPU_TYPE_ENTRY(BSC9130, 9130, 1),
79 CPU_TYPE_ENTRY(BSC9131, 9131, 1),
80 #elif defined(CONFIG_MPC86xx)
81 CPU_TYPE_ENTRY(8610, 8610, 1),
82 CPU_TYPE_ENTRY(8641, 8641, 2),
83 CPU_TYPE_ENTRY(8641D, 8641D, 2),
87 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
88 u32 compute_ppc_cpumask(void)
90 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
92 u32 cluster, mask = 0;
96 cluster = in_be32(&gur->tp_cluster[i++].lower);
97 for (j = 0; j < 4; j++) {
98 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
99 u32 type = in_be32(&gur->tp_ityp[idx]);
101 if (type & TP_ITYP_AV) {
102 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
107 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
111 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
113 * Before chassis genenration 2, the cpumask should be hard-coded.
114 * In case of cpu type unknown or cpumask unset, use 1 as fail save.
116 #define compute_ppc_cpumask() 1
117 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
119 struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
121 struct cpu_type *identify_cpu(u32 ver)
124 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
125 if (cpu_type_list[i].soc_ver == ver)
126 return &cpu_type_list[i];
128 return &cpu_type_unknown;
131 #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
132 #define MPC8xxx_PICFRR_NCPU_SHIFT 8
135 * Return a 32-bit mask indicating which cores are present on this SOC.
139 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
140 struct cpu_type *cpu = gd->cpu;
142 /* better to query feature reporting register than just assume 1 */
143 if (cpu == &cpu_type_unknown)
144 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
145 MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
147 if (cpu->num_cores == 0)
148 return compute_ppc_cpumask();
154 * Return the number of cores on this SOC.
157 struct cpu_type *cpu = gd->cpu;
160 * Report # of cores in terms of the cpu_mask if we haven't
161 * figured out how many there are yet
163 if (cpu->num_cores == 0)
164 return hweight32(cpu_mask());
166 return cpu->num_cores;
170 * Check if the given core ID is valid
172 * Returns zero if it isn't, 1 if it is.
174 int is_core_valid(unsigned int core)
176 return !!((1 << core) & cpu_mask());
185 ver = SVR_SOC_VER(svr);
187 gd->cpu = identify_cpu(ver);
192 /* Once in memory, compute mask & # cores once and save them off */
195 struct cpu_type *cpu = gd->cpu;
197 if (cpu->num_cores == 0) {
198 cpu->mask = cpu_mask();
199 cpu->num_cores = cpu_numcores();
206 * Initializes on-chip ethernet controllers.
207 * to override, implement board_eth_init()
209 int cpu_eth_init(bd_t *bis)
211 #if defined(CONFIG_ETHER_ON_FCC)
215 #if defined(CONFIG_UEC_ETH)
216 uec_standard_init(bis);
219 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
220 tsec_standard_init(bis);
223 #ifdef CONFIG_FMAN_ENET
224 fm_standard_init(bis);