2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /* U-Boot - Startup Code for PowerPC based Embedded Boards
28 * The processor starts at 0x00000100 and the code is executed
29 * from flash. The code is organized to be at an other address
30 * in memory, but as long we don't jump around before relocating,
31 * board_init lies at a quite high address and when the cpu has
32 * jumped there, everything is ok.
33 * This works because the cpu gives the FLASH (CS0) the whole
34 * address space at startup, and board_init lies as a echo of
35 * the flash somewhere up there in the memory map.
37 * board_init will change CS0 to be positioned at the correct
38 * address and (s)dram will be positioned at address 0
40 #include <asm-offsets.h>
45 #define CONFIG_8xx 1 /* needed for Linux kernel header files */
46 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
48 #include <ppc_asm.tmpl>
51 #include <asm/cache.h>
53 #include <asm/u-boot.h>
55 /* We don't want the MMU yet.
58 #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
61 * Set up GOT: Global Offset Table
63 * Use r12 to access the GOT
66 GOT_ENTRY(_GOT2_TABLE_)
67 GOT_ENTRY(_FIXUP_TABLE_)
70 GOT_ENTRY(_start_of_vectors)
71 GOT_ENTRY(_end_of_vectors)
72 GOT_ENTRY(transfer_to_handler)
75 GOT_ENTRY(__bss_end__)
76 GOT_ENTRY(__bss_start)
80 * r3 - 1st arg to board_init(): IMMP pointer
81 * r4 - 2nd arg to board_init(): boot flag
84 .long 0x27051956 /* U-Boot Magic Number */
87 .ascii U_BOOT_VERSION_STRING, "\0"
92 lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
95 /* Initialize machine status; enable machine check interrupt */
96 /*----------------------------------------------------------------------*/
97 li r3, MSR_KERNEL /* Set ME, RI flags */
99 mtspr SRR1, r3 /* Make SRR1 match MSR */
101 mfspr r3, ICR /* clear Interrupt Cause Register */
103 /* Initialize debug port registers */
104 /*----------------------------------------------------------------------*/
105 xor r0, r0, r0 /* Clear R0 */
106 mtspr LCTRL1, r0 /* Initialize debug port regs */
111 /* Reset the caches */
112 /*----------------------------------------------------------------------*/
114 mfspr r3, IC_CST /* Clear error bits */
117 lis r3, IDC_UNALL@h /* Unlock all */
121 lis r3, IDC_INVALL@h /* Invalidate all */
125 lis r3, IDC_DISABLE@h /* Disable data cache */
128 #if !defined(CONFIG_SYS_DELAYED_ICACHE)
129 /* On IP860 and PCU E,
130 * we cannot enable IC yet
132 lis r3, IDC_ENABLE@h /* Enable instruction cache */
136 /* invalidate all tlb's */
137 /*----------------------------------------------------------------------*/
143 * Calculate absolute address in FLASH and jump there
144 *----------------------------------------------------------------------*/
146 lis r3, CONFIG_SYS_MONITOR_BASE@h
147 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
148 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
154 /* initialize some SPRs that are hard to access from C */
155 /*----------------------------------------------------------------------*/
157 lis r3, CONFIG_SYS_IMMR@h /* pass IMMR as arg1 to C routine */
158 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
159 /* Note: R0 is still 0 here */
160 stwu r0, -4(r1) /* clear final stack frame so that */
161 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
164 * Disable serialized ifetch and show cycles
165 * (i.e. set processor to normal mode).
166 * This is also a silicon bug workaround, see errata
172 /* Set up debug mode entry */
174 lis r2, CONFIG_SYS_DER@h
175 ori r2, r2, CONFIG_SYS_DER@l
178 /* let the C-code set up the rest */
180 /* Be careful to keep code relocatable ! */
181 /*----------------------------------------------------------------------*/
183 GET_GOT /* initialize GOT access */
186 bl cpu_init_f /* run low-level CPU init code (from Flash) */
188 bl board_init_f /* run 1st part of board init code (from Flash) */
190 /* NOTREACHED - board_init_f() does not return */
193 .globl _start_of_vectors
197 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
199 /* Data Storage exception. "Never" generated on the 860. */
200 STD_EXCEPTION(0x300, DataStorage, UnknownException)
202 /* Instruction Storage exception. "Never" generated on the 860. */
203 STD_EXCEPTION(0x400, InstStorage, UnknownException)
205 /* External Interrupt exception. */
206 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
208 /* Alignment exception. */
211 EXCEPTION_PROLOG(SRR0, SRR1)
216 addi r3,r1,STACK_FRAME_OVERHEAD
217 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
219 /* Program check exception */
222 EXCEPTION_PROLOG(SRR0, SRR1)
223 addi r3,r1,STACK_FRAME_OVERHEAD
224 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
227 /* No FPU on MPC8xx. This exception is not supposed to happen.
229 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
231 /* I guess we could implement decrementer, and may have
232 * to someday for timekeeping.
234 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
235 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
236 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
237 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
238 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
240 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
241 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
243 /* On the MPC8xx, this is a software emulation interrupt. It occurs
244 * for all unimplemented and illegal instructions.
246 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
248 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
249 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
250 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
251 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
253 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
254 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
255 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
256 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
257 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
258 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
259 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
261 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
262 STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
263 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
264 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
267 .globl _end_of_vectors
274 * This code finishes saving the registers to the exception frame
275 * and jumps to the appropriate handler for the exception.
276 * Register r21 is pointer into trap frame, r1 has new stack pointer.
278 .globl transfer_to_handler
289 andi. r24,r23,0x3f00 /* get vector offset */
293 mtspr SPRG2,r22 /* r1 is now kernel sp */
294 lwz r24,0(r23) /* virtual address of handler */
295 lwz r23,4(r23) /* where to go when done */
300 rfi /* jump to handler, enable MMU */
303 mfmsr r28 /* Disable interrupts */
307 SYNC /* Some chip revs need this... */
322 lwz r2,_NIP(r1) /* Restore environment */
343 .globl icache_disable
346 lis r3, IDC_DISABLE@h
353 srwi r3, r3, 31 /* >>31 => select bit 0 */
362 lis r3, 0x0400 /* Set cache mode with MMU off */
376 .globl dcache_disable
379 lis r3, IDC_DISABLE@h
388 srwi r3, r3, 31 /* >>31 => select bit 0 */
398 * unsigned int get_immr (unsigned int mask)
400 * return (mask ? (IMMR & mask) : IMMR);
404 mr r4,r3 /* save mask */
405 mfspr r3, IMMR /* IMMR */
406 cmpwi 0,r4,0 /* mask != 0 ? */
408 and r3,r3,r4 /* IMMR & mask */
449 /*------------------------------------------------------------------------------*/
452 * void relocate_code (addr_sp, gd, addr_moni)
454 * This "function" does not return, instead it continues in RAM
455 * after relocating the monitor code.
459 * r5 = length in bytes
464 mr r1, r3 /* Set new stack pointer */
465 mr r9, r4 /* Save copy of Global Data pointer */
466 mr r10, r5 /* Save copy of Destination Address */
469 mr r3, r5 /* Destination Address */
470 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
471 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
472 lwz r5, GOT(__init_end)
474 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
479 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
485 /* First our own GOT */
487 /* then the one used by the C code */
497 beq cr1,4f /* In place copy is not necessary */
498 beq 7f /* Protect against 0 count */
517 * Now flush the cache: note that we must start from a cache aligned
518 * address. Otherwise we might miss one cache line.
522 beq 7f /* Always flush prefetch queue in any case */
530 sync /* Wait for all dcbst to complete on bus */
536 7: sync /* Wait for all icbi to complete on bus */
540 * We are done. Do not return, instead branch to second part of board
541 * initialization, now running from RAM.
544 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
551 * Relocation Function, r12 point to got2+0x8000
553 * Adjust got2 pointers, no need to check for 0, this code
554 * already puts a few entries in the table.
556 li r0,__got2_entries@sectoff@l
557 la r3,GOT(_GOT2_TABLE_)
558 lwz r11,GOT(_GOT2_TABLE_)
570 * Now adjust the fixups and the pointers to the fixups
571 * in case we need to move ourselves again.
573 li r0,__fixup_entries@sectoff@l
574 lwz r3,GOT(_FIXUP_TABLE_)
590 * Now clear BSS segment
592 lwz r3,GOT(__bss_start)
593 lwz r4,GOT(__bss_end__)
606 mr r3, r9 /* Global Data pointer */
607 mr r4, r10 /* Destination Address */
611 * Copy exception vector code to low memory
614 * r7: source address, r8: end address, r9: target address
618 mflr r4 /* save link register */
621 lwz r8, GOT(_end_of_vectors)
623 li r9, 0x100 /* reset vector always at 0x100 */
626 bgelr /* return if r7>=r8 - just in case */
636 * relocate `hdlr' and `int_return' entries
638 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
639 li r8, Alignment - _start + EXC_OFF_SYS_RESET
642 addi r7, r7, 0x100 /* next exception vector */
646 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
649 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
652 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
653 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
656 addi r7, r7, 0x100 /* next exception vector */
660 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
661 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
664 addi r7, r7, 0x100 /* next exception vector */
668 mtlr r4 /* restore link register */