3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/compiler.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
19 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
21 #define PROFF_SMC PROFF_SMC1
22 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
24 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
26 #define PROFF_SMC PROFF_SMC2
27 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
29 #endif /* CONFIG_8xx_CONS_SMCx */
31 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
33 #define PROFF_SCC PROFF_SCC1
34 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
36 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
38 #define PROFF_SCC PROFF_SCC2
39 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
41 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
43 #define PROFF_SCC PROFF_SCC3
44 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
46 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
48 #define PROFF_SCC PROFF_SCC4
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
51 #endif /* CONFIG_8xx_CONS_SCCx */
53 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
54 #define CONFIG_SYS_SMC_RXBUFLEN 1
55 #define CONFIG_SYS_MAXIDLE 0
57 #if !defined(CONFIG_SYS_MAXIDLE)
58 #error "you must define CONFIG_SYS_MAXIDLE"
62 typedef volatile struct serialbuffer {
63 cbd_t rxbd; /* Rx BD */
64 cbd_t txbd; /* Tx BD */
65 uint rxindex; /* index for next character to read */
66 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
67 volatile uchar txbuf; /* tx buffers */
70 static void serial_setdivisor(volatile cpm8xx_t *cp)
72 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
74 if(divisor/16>0x1000) {
75 /* bad divisor, assume 50MHz clock and 9600 baud */
76 divisor=(50*1000*1000 + 8*9600)/16/9600;
79 #ifdef CONFIG_SYS_BRGCLK_PRESCALE
80 divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
84 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
86 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
90 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
93 * Minimal serial functions needed to use one of the SMC ports
94 * as serial console interface.
97 static void smc_setbrg (void)
99 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
100 volatile cpm8xx_t *cp = &(im->im_cpm);
102 /* Set up the baud rate generator.
103 * See 8xx_io/commproc.c for details.
108 cp->cp_simode = 0x00000000;
110 serial_setdivisor(cp);
113 static int smc_init (void)
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
117 volatile smc_uart_t *up;
118 volatile cpm8xx_t *cp = &(im->im_cpm);
119 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
120 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
123 volatile serialbuffer_t *rtx;
125 /* initialize pointers to SMC */
127 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
128 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
129 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
130 up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
132 /* Disable relocation */
136 /* Disable transmitter/receiver. */
137 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
140 im->im_siu_conf.sc_sdcr = 1;
142 /* clear error conditions */
143 #ifdef CONFIG_SYS_SDSR
144 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
146 im->im_sdma.sdma_sdsr = 0x83;
149 /* clear SDMA interrupt mask */
150 #ifdef CONFIG_SYS_SDMR
151 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
153 im->im_sdma.sdma_sdmr = 0x00;
156 #if defined(CONFIG_8xx_CONS_SMC1)
157 /* Use Port B for SMC1 instead of other functions. */
158 cp->cp_pbpar |= 0x000000c0;
159 cp->cp_pbdir &= ~0x000000c0;
160 cp->cp_pbodr &= ~0x000000c0;
161 #else /* CONFIG_8xx_CONS_SMC2 */
162 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
163 /* Use Port A for SMC2 instead of other functions. */
164 ip->iop_papar |= 0x00c0;
165 ip->iop_padir &= ~0x00c0;
166 ip->iop_paodr &= ~0x00c0;
167 # else /* must be a 860 then */
168 /* Use Port B for SMC2 instead of other functions.
170 cp->cp_pbpar |= 0x00000c00;
171 cp->cp_pbdir &= ~0x00000c00;
172 cp->cp_pbodr &= ~0x00000c00;
176 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
178 #if defined(CONFIG_8xx_CONS_SMC1)
179 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
181 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
183 #endif /* CONFIG_FADS */
185 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
186 /* Enable Monitor Port Transceiver */
187 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
188 #endif /* CONFIG_RPXLITE */
190 /* Set the physical address of the host memory buffers in
191 * the buffer descriptors.
194 #ifdef CONFIG_SYS_ALLOC_DPRAM
196 * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
198 dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
200 dpaddr = CPM_SERIAL_BASE ;
203 rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
204 /* Allocate space for two buffer descriptors in the DP ram.
205 * For now, this address seems OK, but it may have to
206 * change with newer versions of the firmware.
207 * damm: allocating space after the two buffers for rx/tx data
210 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
211 rtx->rxbd.cbd_sc = 0;
213 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
214 rtx->txbd.cbd_sc = 0;
216 /* Set up the uart parameters in the parameter ram. */
217 up->smc_rbase = dpaddr;
218 up->smc_tbase = dpaddr+sizeof(cbd_t);
219 up->smc_rfcr = SMC_EB;
220 up->smc_tfcr = SMC_EB;
221 #if defined (CONFIG_SYS_SMC_UCODE_PATCH)
222 up->smc_rbptr = up->smc_rbase;
223 up->smc_tbptr = up->smc_tbase;
228 #if defined(CONFIG_MBX)
230 #endif /* CONFIG_MBX */
232 /* Set UART mode, 8 bit, no parity, one stop.
233 * Enable receive and transmit.
235 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
237 /* Mask all interrupts and remove anything pending.
242 #ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
243 /* clock source is PLD */
245 /* set freq to 19200 Baud */
246 *((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
247 /* configure clk4 as input */
248 im->im_ioport.iop_pdpar |= 0x800;
249 im->im_ioport.iop_pddir &= ~0x800;
251 cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
253 /* Set up the baud rate generator */
257 /* Make the first buffer the only buffer. */
258 rtx->txbd.cbd_sc |= BD_SC_WRAP;
259 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
261 /* single/multi character receive. */
262 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
263 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
266 /* Initialize Tx/Rx parameters. */
267 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
270 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
272 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
275 /* Enable transmitter/receiver. */
276 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
282 smc_putc(const char c)
284 volatile smc_uart_t *up;
285 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
286 volatile cpm8xx_t *cpmp = &(im->im_cpm);
287 volatile serialbuffer_t *rtx;
289 #ifdef CONFIG_MODEM_SUPPORT
297 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
298 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
299 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
302 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
304 /* Wait for last character to go. */
306 rtx->txbd.cbd_datlen = 1;
307 rtx->txbd.cbd_sc |= BD_SC_READY;
310 while (rtx->txbd.cbd_sc & BD_SC_READY) {
317 smc_puts (const char *s)
327 volatile smc_uart_t *up;
328 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
329 volatile cpm8xx_t *cpmp = &(im->im_cpm);
330 volatile serialbuffer_t *rtx;
333 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
334 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
335 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
337 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
339 /* Wait for character to show up. */
340 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
343 /* the characters are read one by one,
344 * use the rxindex to know the next char to deliver
346 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
349 /* check if all char are readout, then make prepare for next receive */
350 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
352 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
360 volatile smc_uart_t *up;
361 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
362 volatile cpm8xx_t *cpmp = &(im->im_cpm);
363 volatile serialbuffer_t *rtx;
365 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
366 #ifdef CONFIG_SYS_SMC_UCODE_PATCH
367 up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
370 rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
372 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
375 struct serial_device serial_smc_device =
377 .name = "serial_smc",
380 .setbrg = smc_setbrg,
387 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
389 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
390 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
395 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
396 volatile cpm8xx_t *cp = &(im->im_cpm);
398 /* Set up the baud rate generator.
399 * See 8xx_io/commproc.c for details.
404 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
406 serial_setdivisor(cp);
409 static int scc_init (void)
411 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
413 volatile scc_uart_t *up;
414 volatile cbd_t *tbdf, *rbdf;
415 volatile cpm8xx_t *cp = &(im->im_cpm);
417 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
418 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
421 /* initialize pointers to SCC */
423 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
424 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
426 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
427 { /* Disable Ethernet, enable Serial */
431 c &= ~0x40; /* enable COM3 */
432 c |= 0x80; /* disable Ethernet */
436 cp->cp_pbpar |= 0x2000;
437 cp->cp_pbdat |= 0x2000;
438 cp->cp_pbdir |= 0x2000;
440 #endif /* CONFIG_LWMON */
442 /* Disable transmitter/receiver. */
443 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
445 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
447 * The MPC850 has SCC3 on Port B
449 cp->cp_pbpar |= 0x06;
450 cp->cp_pbdir &= ~0x06;
451 cp->cp_pbodr &= ~0x06;
453 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
455 * Standard configuration for SCC's is on Part A
457 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
458 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
459 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
462 * The IP860 has SCC3 and SCC4 on Port D
464 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
467 /* Allocate space for two buffer descriptors in the DP ram. */
469 #ifdef CONFIG_SYS_ALLOC_DPRAM
470 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
472 dpaddr = CPM_SERIAL2_BASE ;
476 im->im_siu_conf.sc_sdcr = 0x0001;
478 /* Set the physical address of the host memory buffers in
479 * the buffer descriptors.
482 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
483 rbdf->cbd_bufaddr = (uint) (rbdf+2);
486 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
489 /* Set up the baud rate generator. */
492 /* Set up the uart parameters in the parameter ram. */
493 up->scc_genscc.scc_rbase = dpaddr;
494 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
496 /* Initialize Tx/Rx parameters. */
497 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
499 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
501 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
504 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
505 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
507 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
508 up->scc_maxidl = 0; /* disable max idle */
509 up->scc_brkcr = 1; /* send one break character on stop TX */
517 up->scc_char1 = 0x8000;
518 up->scc_char2 = 0x8000;
519 up->scc_char3 = 0x8000;
520 up->scc_char4 = 0x8000;
521 up->scc_char5 = 0x8000;
522 up->scc_char6 = 0x8000;
523 up->scc_char7 = 0x8000;
524 up->scc_char8 = 0x8000;
525 up->scc_rccm = 0xc0ff;
527 /* Set low latency / small fifo. */
528 sp->scc_gsmrh = SCC_GSMRH_RFW;
530 /* Set SCC(x) clock mode to 16x
531 * See 8xx_io/commproc.c for details.
536 /* Set UART mode, clock divider 16 on Tx and Rx */
537 sp->scc_gsmrl &= ~0xF;
539 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
542 sp->scc_psmr |= SCU_PSMR_CL;
544 /* Mask all interrupts and remove anything pending. */
546 sp->scc_scce = 0xffff;
547 sp->scc_dsr = 0x7e7e;
548 sp->scc_psmr = 0x3000;
550 /* Make the first buffer the only buffer. */
551 tbdf->cbd_sc |= BD_SC_WRAP;
552 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
554 /* Enable transmitter/receiver. */
555 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
561 scc_putc(const char c)
563 volatile cbd_t *tbdf;
565 volatile scc_uart_t *up;
566 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
567 volatile cpm8xx_t *cpmp = &(im->im_cpm);
569 #ifdef CONFIG_MODEM_SUPPORT
577 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
579 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
581 /* Wait for last character to go. */
583 buf = (char *)tbdf->cbd_bufaddr;
586 tbdf->cbd_datlen = 1;
587 tbdf->cbd_sc |= BD_SC_READY;
590 while (tbdf->cbd_sc & BD_SC_READY) {
597 scc_puts (const char *s)
607 volatile cbd_t *rbdf;
608 volatile unsigned char *buf;
609 volatile scc_uart_t *up;
610 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
611 volatile cpm8xx_t *cpmp = &(im->im_cpm);
614 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
616 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
618 /* Wait for character to show up. */
619 buf = (unsigned char *)rbdf->cbd_bufaddr;
621 while (rbdf->cbd_sc & BD_SC_EMPTY)
625 rbdf->cbd_sc |= BD_SC_EMPTY;
633 volatile cbd_t *rbdf;
634 volatile scc_uart_t *up;
635 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
636 volatile cpm8xx_t *cpmp = &(im->im_cpm);
638 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
640 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
642 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
645 struct serial_device serial_scc_device =
647 .name = "serial_scc",
650 .setbrg = scc_setbrg,
657 #endif /* CONFIG_8xx_CONS_SCCx */
659 __weak struct serial_device *default_serial_console(void)
661 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
662 return &serial_smc_device;
664 return &serial_scc_device;
668 void mpc8xx_serial_initialize(void)
670 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
671 serial_register(&serial_smc_device);
673 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
674 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
675 serial_register(&serial_scc_device);
679 #ifdef CONFIG_MODEM_SUPPORT
680 void disable_putc(void)
685 void enable_putc(void)
691 #if defined(CONFIG_CMD_KGDB)
694 kgdb_serial_init(void)
698 if (strcmp(default_serial_console()->name, "serial_smc") == 0)
700 #if defined(CONFIG_8xx_CONS_SMC1)
702 #elif defined(CONFIG_8xx_CONS_SMC2)
706 else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
708 #if defined(CONFIG_8xx_CONS_SCC1)
710 #elif defined(CONFIG_8xx_CONS_SCC2)
712 #elif defined(CONFIG_8xx_CONS_SCC3)
714 #elif defined(CONFIG_8xx_CONS_SCC4)
721 serial_printf("[on %s%d] ", default_serial_console()->name, i);
732 putDebugStr (const char *str)
740 return serial_getc();
744 kgdb_interruptible (int yes)
750 #endif /* CONFIG_8xx_CONS_NONE */