4 * Basic ET HW initialization and packet RX/TX routines
6 * NOTE <<<IMPORTANT: PLEASE READ>>>:
7 * Do not cache Rx/Tx buffers!
11 * MPC823 <-> MC68160 Connections:
13 * Setup MPC823 to work with MC68160 Enhanced Ethernet
14 * Serial Tranceiver as follows:
16 * MPC823 Signal MC68160 Comments
17 * ------ ------ ------- --------
18 * PA-12 ETHTX --------> TX Eth. Port Transmit Data
19 * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
20 * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
21 * PA-13 ETHRX <-------- RX Eth. Port Receive Data
22 * PC-8 E_RENA <-------- RENA Eth. Receive Enable
23 * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
24 * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
26 * FADS Board Signal MC68160 Comments
27 * ----------------- ------- --------
28 * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
29 * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
30 * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
31 * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
41 #if defined(CONFIG_CMD_NET) && defined(SCC_ENET)
43 /* Ethernet Transmit and Receive Buffers */
44 #define DBUF_LENGTH 1520
48 #define TOUT_LOOP 10000 /* 10 ms to have a packet sent */
50 static char txbuf[DBUF_LENGTH];
52 static uint rxIdx; /* index of the current RX buffer */
53 static uint txIdx; /* index of the current TX buffer */
56 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
57 * immr->udata_bd address on Dual-Port RAM
58 * Provide for Double Buffering
61 typedef volatile struct CommonBufferDescriptor {
62 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
63 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
68 static int scc_send(struct eth_device *dev, void *packet, int length);
69 static int scc_recv(struct eth_device* dev);
70 static int scc_init (struct eth_device* dev, bd_t * bd);
71 static void scc_halt(struct eth_device* dev);
73 int scc_initialize(bd_t *bis)
75 struct eth_device* dev;
77 dev = (struct eth_device*) malloc(sizeof *dev);
78 memset(dev, 0, sizeof *dev);
80 sprintf(dev->name, "SCC");
93 static int scc_send(struct eth_device *dev, void *packet, int length)
97 volatile char *in, *out;
104 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
105 out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
107 for(i = 0; i < length; i++) {
110 rtx->txbd[txIdx].cbd_datlen = length;
111 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
112 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
115 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
117 i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
119 /* wrap around buffer index when necessary */
120 if (txIdx >= TX_BUF_CNT) txIdx = 0;
123 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
124 udelay (1); /* will also trigger Wd if needed */
127 if (j>=TOUT_LOOP) printf("TX not ready\n");
128 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
129 rtx->txbd[txIdx].cbd_datlen = length;
130 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
131 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
132 udelay (1); /* will also trigger Wd if needed */
135 if (j>=TOUT_LOOP) printf("TX timeout\n");
137 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
139 i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
143 static int scc_recv (struct eth_device *dev)
148 /* section 16.9.23.2 */
149 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
151 break; /* nothing received - leave for() loop */
154 length = rtx->rxbd[rxIdx].cbd_datlen;
156 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
158 printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
161 /* Pass the packet up to the protocol layers. */
162 NetReceive (NetRxPackets[rxIdx], length - 4);
166 /* Give the buffer back to the SCC. */
167 rtx->rxbd[rxIdx].cbd_datlen = 0;
169 /* wrap around buffer index when necessary */
170 if ((rxIdx + 1) >= PKTBUFSRX) {
171 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
172 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
175 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
182 /**************************************************************
184 * SCC Ethernet Initialization Routine
186 *************************************************************/
188 static int scc_init (struct eth_device *dev, bd_t * bis)
192 scc_enet_t *pram_ptr;
194 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
196 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
202 #ifdef CONFIG_SYS_ALLOC_DPRAM
203 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
204 dpram_alloc_align (sizeof (RTXBD), 8));
206 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
210 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
211 /* Configure port A pins for Txd and Rxd.
213 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
214 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
215 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
216 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
217 /* Configure port B pins for Txd and Rxd.
219 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
220 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
221 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
223 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
226 #if defined(PC_ENET_LBK)
227 /* Configure port C pins to disable External Loopback
229 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
230 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
231 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
232 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
233 #endif /* PC_ENET_LBK */
235 /* Configure port C pins to enable CLSN and RENA.
237 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
238 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
239 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
241 /* Configure port A for TCLK and RCLK.
243 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
244 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
247 * Configure Serial Interface clock routing -- see section 16.7.5.3
248 * First, clear all SCC bits to zero, then set the ones we want.
251 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
252 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
256 * Initialize SDCR -- see section 16.9.23.7
257 * SDMA configuration register
259 immr->im_siu_conf.sc_sdcr = 0x01;
263 * Setup SCC Ethernet Parameter RAM
266 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
267 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
269 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
271 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
272 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
275 * Setup Receiver Buffer Descriptors (13.14.24.18)
280 for (i = 0; i < PKTBUFSRX; i++) {
281 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
282 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
283 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
286 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
289 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
291 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
294 for (i = 0; i < TX_BUF_CNT; i++) {
295 rtx->txbd[i].cbd_sc =
296 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
297 rtx->txbd[i].cbd_datlen = 0; /* Reset */
298 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
301 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
304 * Enter Command: Initialize Rx Params for SCC
307 do { /* Spin until ready to issue command */
309 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
311 immr->im_cpm.cp_cpcr =
312 ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
313 do { /* Spin until command processed */
315 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
318 * Ethernet Specific Parameter RAM
319 * see table 13-16, pg. 660,
320 * pg. 681 (example with suggested settings)
323 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
324 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
325 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
326 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
327 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
328 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
330 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
331 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
332 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
334 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
335 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
337 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
338 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
339 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
340 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
342 #define ea eth_get_dev()->enetaddr
343 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
344 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
345 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
348 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
349 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
350 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
351 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
352 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
353 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
354 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
355 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
358 * Enter Command: Initialize Tx Params for SCC
361 do { /* Spin until ready to issue command */
363 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
365 immr->im_cpm.cp_cpcr =
366 ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
367 do { /* Spin until command processed */
369 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
372 * Mask all Events in SCCM - we use polling mode
374 immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
377 * Clear Events in SCCE -- Clear bits by writing 1's
380 immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
384 * Initialize GSMR High 32-Bits
385 * Settings: Normal Mode
388 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
391 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
395 * TPP = Repeating 10's
399 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
402 SCC_GSMRL_MODE_ENET);
405 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
408 immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
411 * Initialize the PSMR
414 * NIB = Begin searching for SFD 22 bits after RENA
415 * FDE = Full Duplex Enable
416 * LPB = Loopback Enable (Needed when FDE is set)
417 * BRO = Reject broadcast packets
418 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
420 immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
422 #if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
423 SCC_PSMR_FDE | SCC_PSMR_LPB |
425 #if defined(CONFIG_SCC_ENET_NO_BROADCAST)
428 #if defined(CONFIG_SCC_ENET_PROMISCOUS)
434 * Configure Ethernet TENA Signal
437 #if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
438 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
439 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
440 #elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
441 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
442 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
444 #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
448 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
451 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
452 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
458 static void scc_halt (struct eth_device *dev)
460 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
462 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
463 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
465 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
471 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
473 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
474 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);