3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Back ported to the 8xx platform (from the 8260 platform) by
27 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
32 #ifdef CONFIG_HARD_I2C
40 DECLARE_GLOBAL_DATA_PTR;
42 /* define to enable debug messages */
45 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
46 #define TOUT_LOOP 1000000
50 #define MAX_TX_SPACE 256
51 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
53 typedef struct I2C_BD {
54 unsigned short status;
55 unsigned short length;
59 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
61 #define BD_I2C_TX_CL 0x0001 /* collision error */
62 #define BD_I2C_TX_UN 0x0002 /* underflow error */
63 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
64 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
66 #define BD_I2C_RX_ERR BD_SC_OV
68 typedef void (*i2c_ecb_t) (int, int); /* error callback function */
70 /* This structure keeps track of the bd and buffer space usage. */
71 typedef struct i2c_state {
72 int rx_idx; /* index to next free Rx BD */
73 int tx_idx; /* index to next free Tx BD */
74 void *rxbd; /* pointer to next free Rx BD */
75 void *txbd; /* pointer to next free Tx BD */
76 int tx_space; /* number of Tx bytes left */
77 unsigned char *tx_buf; /* pointer to free Tx area */
78 i2c_ecb_t err_cb; /* error callback function */
82 /* flags for i2c_send() and i2c_receive() */
83 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
84 #define I2CF_START_COND 0x02 /* tx: generate start condition */
85 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
88 #define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
89 #define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
90 #define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
91 #define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
93 /* error callback flags */
94 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
95 #define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
96 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
97 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
98 #define I2CECB_TX_CL 0x01 /* transmit collision error */
99 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
100 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
101 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
102 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
105 #define PRINTD(x) printf x
111 * Returns the best value of I2BRG to meet desired clock speed of I2C with
112 * input parameters (clock speed, filter, and predivider value).
113 * It returns computer speed value and the difference between it and desired
117 i2c_roundrate(int hz, int speed, int filter, int modval,
118 int *brgval, int *totspeed)
120 int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
122 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
123 hz, speed, filter, modval));
125 div = moddiv * speed;
126 brgdiv = (hz + div - 1) / div;
128 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
130 *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
132 if ((*brgval < 0) || (*brgval > 255)) {
133 PRINTD(("\t\trejected brgval=%d\n", *brgval));
137 brgdiv = 2 * (*brgval + 3 + (2 * filter));
138 div = moddiv * brgdiv;
139 *totspeed = hz / div;
141 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
147 * Sets the I2C clock predivider and divider to meet required clock speed.
149 static int i2c_setrate(int hz, int speed)
151 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
152 volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
155 bestspeed_diff = speed,
156 bestspeed_brgval = 0,
157 bestspeed_modval = 0,
158 bestspeed_filter = 0,
160 filter = 0; /* Use this fixed value */
162 for (modval = 0; modval < 4; modval++) {
164 (hz, speed, filter, modval, &brgval, &totspeed) == 0) {
165 int diff = speed - totspeed;
167 if ((diff >= 0) && (diff < bestspeed_diff)) {
168 bestspeed_diff = diff;
169 bestspeed_modval = modval;
170 bestspeed_brgval = brgval;
171 bestspeed_filter = filter;
176 PRINTD (("[I2C] Best is:\n"));
177 PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
186 ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
187 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
189 PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
195 void i2c_init(int speed, int slaveaddr)
197 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
198 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
199 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
200 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
202 volatile I2C_BD *rxbd, *txbd;
205 #ifdef CONFIG_SYS_I2C_INIT_BOARD
206 /* call board specific i2c bus reset routine before accessing the */
207 /* environment, which might be in a chip on that bus. For details */
208 /* about this problem see doc/I2C_Edge_Conditions. */
212 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
213 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
215 /* Disable relocation */
219 #ifdef CONFIG_SYS_ALLOC_DPRAM
220 dpaddr = iip->iic_rbase;
222 /* need to allocate dual port ram */
223 dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
224 (NUM_TX_BDS * sizeof(I2C_BD)) +
228 dpaddr = CPM_I2C_BASE;
232 * initialise data in dual port ram:
234 * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
235 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
236 * tx buffer (MAX_TX_SPACE bytes)
240 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
242 /* Initialize Port B I2C pins. */
243 cp->cp_pbpar |= 0x00000030;
244 cp->cp_pbdir |= 0x00000030;
245 cp->cp_pbodr |= 0x00000030;
247 /* Disable interrupts */
248 i2c->i2c_i2mod = 0x00;
249 i2c->i2c_i2cmr = 0x00;
250 i2c->i2c_i2cer = 0xff;
251 i2c->i2c_i2add = slaveaddr;
254 * Set the I2C BRG Clock division factor from desired i2c rate
255 * and current CPU rate (we assume sccr dfbgr field is 0;
256 * divide BRGCLK by 1)
258 PRINTD(("[I2C] Setting rate...\n"));
259 i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
261 /* Set I2C controller in master mode */
262 i2c->i2c_i2com = 0x01;
264 /* Set SDMA bus arbitration level to 5 (SDCR) */
265 immap->im_siu_conf.sc_sdcr = 0x0001;
267 /* Initialize Tx/Rx parameters */
268 iip->iic_rbase = rbase;
269 iip->iic_tbase = tbase;
270 rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
271 txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
273 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
274 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
275 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
276 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
278 /* Set big endian byte order */
279 iip->iic_tfcr = 0x10;
280 iip->iic_rfcr = 0x10;
282 /* Set maximum receive size. */
283 iip->iic_mrblr = I2C_RXTX_LEN;
285 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
287 * Initialize required parameters if using microcode patch.
289 iip->iic_rbptr = iip->iic_rbase;
290 iip->iic_tbptr = iip->iic_tbase;
294 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
296 __asm__ __volatile__("eieio");
297 } while (cp->cp_cpcr & CPM_CR_FLG);
300 /* Clear events and interrupts */
301 i2c->i2c_i2cer = 0xff;
302 i2c->i2c_i2cmr = 0x00;
305 static void i2c_newio(i2c_state_t *state)
307 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
308 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
309 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
311 PRINTD(("[I2C] i2c_newio\n"));
313 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
314 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
318 state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
319 state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
320 state->tx_space = MAX_TX_SPACE;
321 state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
322 state->err_cb = NULL;
324 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
325 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
326 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
328 /* clear the buffer memory */
329 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
333 i2c_send(i2c_state_t *state,
334 unsigned char address,
335 unsigned char secondary_address,
336 unsigned int flags, unsigned short size, unsigned char *dataout)
338 volatile I2C_BD *txbd;
341 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
342 address, secondary_address, flags, size));
344 /* trying to send message larger than BD */
345 if (size > I2C_RXTX_LEN)
346 return I2CERR_MSG_TOO_LONG;
348 /* no more free bds */
349 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
350 return I2CERR_NO_BUFFERS;
352 txbd = (I2C_BD *) state->txbd;
353 txbd->addr = state->tx_buf;
355 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
357 if (flags & I2CF_START_COND) {
358 PRINTD(("[I2C] Formatting addresses...\n"));
359 if (flags & I2CF_ENABLE_SECONDARY) {
360 /* Length of msg + dest addr */
361 txbd->length = size + 2;
363 txbd->addr[0] = address << 1;
364 txbd->addr[1] = secondary_address;
367 /* Length of msg + dest addr */
368 txbd->length = size + 1;
369 /* Write dest addr to BD */
370 txbd->addr[0] = address << 1;
374 txbd->length = size; /* Length of message */
379 txbd->status = BD_SC_READY;
380 if (flags & I2CF_START_COND)
381 txbd->status |= BD_I2C_TX_START;
382 if (flags & I2CF_STOP_COND)
383 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
385 /* Copy data to send into buffer */
386 PRINTD(("[I2C] copy data...\n"));
387 for(j = 0; j < size; i++, j++)
388 txbd->addr[i] = dataout[j];
390 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
397 state->tx_buf += txbd->length;
398 state->tx_space -= txbd->length;
400 state->txbd = (void *) (txbd + 1);
406 i2c_receive(i2c_state_t *state,
407 unsigned char address,
408 unsigned char secondary_address,
410 unsigned short size_to_expect, unsigned char *datain)
412 volatile I2C_BD *rxbd, *txbd;
414 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n",
415 address, secondary_address, flags));
417 /* Expected to receive too much */
418 if (size_to_expect > I2C_RXTX_LEN)
419 return I2CERR_MSG_TOO_LONG;
421 /* no more free bds */
422 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
423 || state->tx_space < 2)
424 return I2CERR_NO_BUFFERS;
426 rxbd = (I2C_BD *) state->rxbd;
427 txbd = (I2C_BD *) state->txbd;
429 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
430 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
432 txbd->addr = state->tx_buf;
434 /* set up TXBD for destination address */
435 if (flags & I2CF_ENABLE_SECONDARY) {
437 txbd->addr[0] = address << 1; /* Write data */
438 txbd->addr[1] = secondary_address; /* Internal address */
439 txbd->status = BD_SC_READY;
441 txbd->length = 1 + size_to_expect;
442 txbd->addr[0] = (address << 1) | 0x01;
443 txbd->status = BD_SC_READY;
444 memset(&txbd->addr[1], 0, txbd->length);
447 /* set up rxbd for reception */
448 rxbd->status = BD_SC_EMPTY;
449 rxbd->length = size_to_expect;
452 txbd->status |= BD_I2C_TX_START;
453 if (flags & I2CF_STOP_COND) {
454 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
455 rxbd->status |= BD_SC_WRAP;
458 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
463 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
470 state->tx_buf += txbd->length;
471 state->tx_space -= txbd->length;
473 state->txbd = (void *) (txbd + 1);
475 state->rxbd = (void *) (rxbd + 1);
481 static int i2c_doio(i2c_state_t *state)
483 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
484 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
485 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
486 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
487 volatile I2C_BD *txbd, *rxbd;
490 PRINTD(("[I2C] i2c_doio\n"));
492 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
493 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
496 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
497 PRINTD(("[I2C] No I/O is queued\n"));
498 return I2CERR_QUEUE_EMPTY;
501 iip->iic_rbptr = iip->iic_rbase;
502 iip->iic_tbptr = iip->iic_tbase;
505 PRINTD(("[I2C] Enabling I2C...\n"));
506 i2c->i2c_i2mod |= 0x01;
508 /* Begin transmission */
509 i2c->i2c_i2com |= 0x80;
511 /* Loop until transmit & receive completed */
513 if (state->tx_idx > 0) {
514 txbd = ((I2C_BD*)state->txbd) - 1;
515 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
516 while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
520 __asm__ __volatile__("eieio");
524 if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
525 rxbd = ((I2C_BD*)state->rxbd) - 1;
526 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
527 while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
531 __asm__ __volatile__("eieio");
536 i2c->i2c_i2mod &= ~0x01;
538 if (state->err_cb != NULL) {
542 * if we have an error callback function, look at the
543 * error bits in the bd status and pass them back
546 if ((n = state->tx_idx) > 0) {
547 for (i = 0; i < n; i++) {
548 txbd = ((I2C_BD *) state->txbd) - (n - i);
549 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
550 (*state->err_cb) (I2CECB_TX_ERR | b,
555 if ((n = state->rx_idx) > 0) {
556 for (i = 0; i < n; i++) {
557 rxbd = ((I2C_BD *) state->rxbd) - (n - i);
558 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
559 (*state->err_cb) (I2CECB_RX_ERR | b,
565 (*state->err_cb) (I2CECB_TIMEOUT, 0);
568 return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
571 static int had_tx_nak;
573 static void i2c_test_callback(int flags, int xnum)
575 if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
579 int i2c_probe(uchar chip)
585 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
589 state.err_cb = i2c_test_callback;
592 rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
598 rc = i2c_doio(&state);
600 if ((rc != 0) && (rc != I2CERR_TIMEOUT))
606 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
616 xaddr[0] = (addr >> 24) & 0xFF;
617 xaddr[1] = (addr >> 16) & 0xFF;
618 xaddr[2] = (addr >> 8) & 0xFF;
619 xaddr[3] = addr & 0xFF;
621 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
623 * EEPROM chips that implement "address overflow" are ones like
624 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
625 * extra bits end up in the "chip address" bit slots. This makes
626 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
628 * Note that we consider the length of the address field to still
629 * be one byte because the extra address bits are hidden in the
632 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
637 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
640 printf("i2c_read: i2c_send failed (%d)\n", rc);
644 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
646 printf("i2c_read: i2c_receive failed (%d)\n", rc);
650 rc = i2c_doio(&state);
652 printf("i2c_read: i2c_doio failed (%d)\n", rc);
658 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
664 xaddr[0] = (addr >> 24) & 0xFF;
665 xaddr[1] = (addr >> 16) & 0xFF;
666 xaddr[2] = (addr >> 8) & 0xFF;
667 xaddr[3] = addr & 0xFF;
669 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
671 * EEPROM chips that implement "address overflow" are ones like
672 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
673 * extra bits end up in the "chip address" bit slots. This makes
674 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
676 * Note that we consider the length of the address field to still
677 * be one byte because the extra address bits are hidden in the
680 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
685 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
688 printf("i2c_write: first i2c_send failed (%d)\n", rc);
692 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
694 printf("i2c_write: second i2c_send failed (%d)\n", rc);
698 rc = i2c_doio(&state);
700 printf("i2c_write: i2c_doio failed (%d)\n", rc);
706 #endif /* CONFIG_HARD_I2C */