3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Back ported to the 8xx platform (from the 8260 platform) by
27 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
32 #ifdef CONFIG_HARD_I2C
40 DECLARE_GLOBAL_DATA_PTR;
42 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
43 #define TOUT_LOOP 1000000
47 #define MAX_TX_SPACE 256
48 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
50 typedef struct I2C_BD {
51 unsigned short status;
52 unsigned short length;
56 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
58 #define BD_I2C_TX_CL 0x0001 /* collision error */
59 #define BD_I2C_TX_UN 0x0002 /* underflow error */
60 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
61 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
63 #define BD_I2C_RX_ERR BD_SC_OV
65 typedef void (*i2c_ecb_t) (int, int); /* error callback function */
67 /* This structure keeps track of the bd and buffer space usage. */
68 typedef struct i2c_state {
69 int rx_idx; /* index to next free Rx BD */
70 int tx_idx; /* index to next free Tx BD */
71 void *rxbd; /* pointer to next free Rx BD */
72 void *txbd; /* pointer to next free Tx BD */
73 int tx_space; /* number of Tx bytes left */
74 unsigned char *tx_buf; /* pointer to free Tx area */
75 i2c_ecb_t err_cb; /* error callback function */
79 /* flags for i2c_send() and i2c_receive() */
80 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
81 #define I2CF_START_COND 0x02 /* tx: generate start condition */
82 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
85 #define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
86 #define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
87 #define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
88 #define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
90 /* error callback flags */
91 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
92 #define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
93 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
94 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
95 #define I2CECB_TX_CL 0x01 /* transmit collision error */
96 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
97 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
98 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
99 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
102 * Returns the best value of I2BRG to meet desired clock speed of I2C with
103 * input parameters (clock speed, filter, and predivider value).
104 * It returns computer speed value and the difference between it and desired
108 i2c_roundrate(int hz, int speed, int filter, int modval,
109 int *brgval, int *totspeed)
111 int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
113 debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
114 hz, speed, filter, modval);
116 div = moddiv * speed;
117 brgdiv = (hz + div - 1) / div;
119 debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
121 *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
123 if ((*brgval < 0) || (*brgval > 255)) {
124 debug("\t\trejected brgval=%d\n", *brgval);
128 brgdiv = 2 * (*brgval + 3 + (2 * filter));
129 div = moddiv * brgdiv;
130 *totspeed = hz / div;
132 debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
138 * Sets the I2C clock predivider and divider to meet required clock speed.
140 static int i2c_setrate(int hz, int speed)
142 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
143 volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
146 bestspeed_diff = speed,
147 bestspeed_brgval = 0,
148 bestspeed_modval = 0,
149 bestspeed_filter = 0,
151 filter = 0; /* Use this fixed value */
153 for (modval = 0; modval < 4; modval++) {
155 (hz, speed, filter, modval, &brgval, &totspeed) == 0) {
156 int diff = speed - totspeed;
158 if ((diff >= 0) && (diff < bestspeed_diff)) {
159 bestspeed_diff = diff;
160 bestspeed_modval = modval;
161 bestspeed_brgval = brgval;
162 bestspeed_filter = filter;
167 debug("[I2C] Best is:\n");
168 debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
177 ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
178 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
180 debug("[I2C] i2mod=%08x i2brg=%08x\n",
187 void i2c_init(int speed, int slaveaddr)
189 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
190 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
191 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
192 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
194 volatile I2C_BD *rxbd, *txbd;
197 #ifdef CONFIG_SYS_I2C_INIT_BOARD
198 /* call board specific i2c bus reset routine before accessing the */
199 /* environment, which might be in a chip on that bus. For details */
200 /* about this problem see doc/I2C_Edge_Conditions. */
204 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
205 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
207 /* Disable relocation */
211 #ifdef CONFIG_SYS_ALLOC_DPRAM
212 dpaddr = iip->iic_rbase;
214 /* need to allocate dual port ram */
215 dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
216 (NUM_TX_BDS * sizeof(I2C_BD)) +
220 dpaddr = CPM_I2C_BASE;
224 * initialise data in dual port ram:
226 * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
227 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
228 * tx buffer (MAX_TX_SPACE bytes)
232 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
234 /* Initialize Port B I2C pins. */
235 cp->cp_pbpar |= 0x00000030;
236 cp->cp_pbdir |= 0x00000030;
237 cp->cp_pbodr |= 0x00000030;
239 /* Disable interrupts */
240 i2c->i2c_i2mod = 0x00;
241 i2c->i2c_i2cmr = 0x00;
242 i2c->i2c_i2cer = 0xff;
243 i2c->i2c_i2add = slaveaddr;
246 * Set the I2C BRG Clock division factor from desired i2c rate
247 * and current CPU rate (we assume sccr dfbgr field is 0;
248 * divide BRGCLK by 1)
250 debug("[I2C] Setting rate...\n");
251 i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
253 /* Set I2C controller in master mode */
254 i2c->i2c_i2com = 0x01;
256 /* Set SDMA bus arbitration level to 5 (SDCR) */
257 immap->im_siu_conf.sc_sdcr = 0x0001;
259 /* Initialize Tx/Rx parameters */
260 iip->iic_rbase = rbase;
261 iip->iic_tbase = tbase;
262 rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
263 txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
265 debug("[I2C] rbase = %04x\n", iip->iic_rbase);
266 debug("[I2C] tbase = %04x\n", iip->iic_tbase);
267 debug("[I2C] rxbd = %08x\n", (int)rxbd);
268 debug("[I2C] txbd = %08x\n", (int)txbd);
270 /* Set big endian byte order */
271 iip->iic_tfcr = 0x10;
272 iip->iic_rfcr = 0x10;
274 /* Set maximum receive size. */
275 iip->iic_mrblr = I2C_RXTX_LEN;
277 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
279 * Initialize required parameters if using microcode patch.
281 iip->iic_rbptr = iip->iic_rbase;
282 iip->iic_tbptr = iip->iic_tbase;
286 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
288 __asm__ __volatile__("eieio");
289 } while (cp->cp_cpcr & CPM_CR_FLG);
292 /* Clear events and interrupts */
293 i2c->i2c_i2cer = 0xff;
294 i2c->i2c_i2cmr = 0x00;
297 static void i2c_newio(i2c_state_t *state)
299 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
300 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
301 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
303 debug("[I2C] i2c_newio\n");
305 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
306 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
310 state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
311 state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
312 state->tx_space = MAX_TX_SPACE;
313 state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
314 state->err_cb = NULL;
316 debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
317 debug("[I2C] txbd = %08x\n", (int)state->txbd);
318 debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
320 /* clear the buffer memory */
321 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
325 i2c_send(i2c_state_t *state,
326 unsigned char address,
327 unsigned char secondary_address,
328 unsigned int flags, unsigned short size, unsigned char *dataout)
330 volatile I2C_BD *txbd;
333 debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
334 address, secondary_address, flags, size);
336 /* trying to send message larger than BD */
337 if (size > I2C_RXTX_LEN)
338 return I2CERR_MSG_TOO_LONG;
340 /* no more free bds */
341 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
342 return I2CERR_NO_BUFFERS;
344 txbd = (I2C_BD *) state->txbd;
345 txbd->addr = state->tx_buf;
347 debug("[I2C] txbd = %08x\n", (int)txbd);
349 if (flags & I2CF_START_COND) {
350 debug("[I2C] Formatting addresses...\n");
351 if (flags & I2CF_ENABLE_SECONDARY) {
352 /* Length of msg + dest addr */
353 txbd->length = size + 2;
355 txbd->addr[0] = address << 1;
356 txbd->addr[1] = secondary_address;
359 /* Length of msg + dest addr */
360 txbd->length = size + 1;
361 /* Write dest addr to BD */
362 txbd->addr[0] = address << 1;
366 txbd->length = size; /* Length of message */
371 txbd->status = BD_SC_READY;
372 if (flags & I2CF_START_COND)
373 txbd->status |= BD_I2C_TX_START;
374 if (flags & I2CF_STOP_COND)
375 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
377 /* Copy data to send into buffer */
378 debug("[I2C] copy data...\n");
379 for(j = 0; j < size; i++, j++)
380 txbd->addr[i] = dataout[j];
382 debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
389 state->tx_buf += txbd->length;
390 state->tx_space -= txbd->length;
392 state->txbd = (void *) (txbd + 1);
398 i2c_receive(i2c_state_t *state,
399 unsigned char address,
400 unsigned char secondary_address,
402 unsigned short size_to_expect, unsigned char *datain)
404 volatile I2C_BD *rxbd, *txbd;
406 debug("[I2C] i2c_receive %02d %02d %02d\n",
407 address, secondary_address, flags);
409 /* Expected to receive too much */
410 if (size_to_expect > I2C_RXTX_LEN)
411 return I2CERR_MSG_TOO_LONG;
413 /* no more free bds */
414 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
415 || state->tx_space < 2)
416 return I2CERR_NO_BUFFERS;
418 rxbd = (I2C_BD *) state->rxbd;
419 txbd = (I2C_BD *) state->txbd;
421 debug("[I2C] rxbd = %08x\n", (int)rxbd);
422 debug("[I2C] txbd = %08x\n", (int)txbd);
424 txbd->addr = state->tx_buf;
426 /* set up TXBD for destination address */
427 if (flags & I2CF_ENABLE_SECONDARY) {
429 txbd->addr[0] = address << 1; /* Write data */
430 txbd->addr[1] = secondary_address; /* Internal address */
431 txbd->status = BD_SC_READY;
433 txbd->length = 1 + size_to_expect;
434 txbd->addr[0] = (address << 1) | 0x01;
435 txbd->status = BD_SC_READY;
436 memset(&txbd->addr[1], 0, txbd->length);
439 /* set up rxbd for reception */
440 rxbd->status = BD_SC_EMPTY;
441 rxbd->length = size_to_expect;
444 txbd->status |= BD_I2C_TX_START;
445 if (flags & I2CF_STOP_COND) {
446 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
447 rxbd->status |= BD_SC_WRAP;
450 debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
455 debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
462 state->tx_buf += txbd->length;
463 state->tx_space -= txbd->length;
465 state->txbd = (void *) (txbd + 1);
467 state->rxbd = (void *) (rxbd + 1);
473 static int i2c_doio(i2c_state_t *state)
475 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
476 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
477 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
478 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
479 volatile I2C_BD *txbd, *rxbd;
482 debug("[I2C] i2c_doio\n");
484 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
485 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
488 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
489 debug("[I2C] No I/O is queued\n");
490 return I2CERR_QUEUE_EMPTY;
493 iip->iic_rbptr = iip->iic_rbase;
494 iip->iic_tbptr = iip->iic_tbase;
497 debug("[I2C] Enabling I2C...\n");
498 i2c->i2c_i2mod |= 0x01;
500 /* Begin transmission */
501 i2c->i2c_i2com |= 0x80;
503 /* Loop until transmit & receive completed */
505 if (state->tx_idx > 0) {
506 txbd = ((I2C_BD*)state->txbd) - 1;
508 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
511 while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
515 __asm__ __volatile__("eieio");
519 if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
520 rxbd = ((I2C_BD*)state->rxbd) - 1;
522 debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
525 while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
529 __asm__ __volatile__("eieio");
534 i2c->i2c_i2mod &= ~0x01;
536 if (state->err_cb != NULL) {
540 * if we have an error callback function, look at the
541 * error bits in the bd status and pass them back
544 if ((n = state->tx_idx) > 0) {
545 for (i = 0; i < n; i++) {
546 txbd = ((I2C_BD *) state->txbd) - (n - i);
547 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
548 (*state->err_cb) (I2CECB_TX_ERR | b,
553 if ((n = state->rx_idx) > 0) {
554 for (i = 0; i < n; i++) {
555 rxbd = ((I2C_BD *) state->rxbd) - (n - i);
556 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
557 (*state->err_cb) (I2CECB_RX_ERR | b,
563 (*state->err_cb) (I2CECB_TIMEOUT, 0);
566 return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
569 static int had_tx_nak;
571 static void i2c_test_callback(int flags, int xnum)
573 if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
577 int i2c_probe(uchar chip)
583 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
587 state.err_cb = i2c_test_callback;
590 rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
596 rc = i2c_doio(&state);
598 if ((rc != 0) && (rc != I2CERR_TIMEOUT))
604 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
614 xaddr[0] = (addr >> 24) & 0xFF;
615 xaddr[1] = (addr >> 16) & 0xFF;
616 xaddr[2] = (addr >> 8) & 0xFF;
617 xaddr[3] = addr & 0xFF;
619 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
621 * EEPROM chips that implement "address overflow" are ones like
622 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
623 * extra bits end up in the "chip address" bit slots. This makes
624 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
626 * Note that we consider the length of the address field to still
627 * be one byte because the extra address bits are hidden in the
630 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
635 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
638 printf("i2c_read: i2c_send failed (%d)\n", rc);
642 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
644 printf("i2c_read: i2c_receive failed (%d)\n", rc);
648 rc = i2c_doio(&state);
650 printf("i2c_read: i2c_doio failed (%d)\n", rc);
656 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
662 xaddr[0] = (addr >> 24) & 0xFF;
663 xaddr[1] = (addr >> 16) & 0xFF;
664 xaddr[2] = (addr >> 8) & 0xFF;
665 xaddr[3] = addr & 0xFF;
667 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
669 * EEPROM chips that implement "address overflow" are ones like
670 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
671 * extra bits end up in the "chip address" bit slots. This makes
672 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
674 * Note that we consider the length of the address field to still
675 * be one byte because the extra address bits are hidden in the
678 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
683 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
686 printf("i2c_write: first i2c_send failed (%d)\n", rc);
690 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
692 printf("i2c_write: second i2c_send failed (%d)\n", rc);
696 rc = i2c_doio(&state);
698 printf("i2c_write: i2c_doio failed (%d)\n", rc);
704 #endif /* CONFIG_HARD_I2C */