arch/powerpc/cpu/mpc8xx/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  *
  10  * Back ported to the 8xx platform (from the 8260 platform) by
  11  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  12  */
  13
  14 #include <common.h>
  15 #include <console.h>
  16
  17 #ifdef CONFIG_HARD_I2C
  18
  19 #include <commproc.h>
  20 #include <i2c.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
  25 #define TOUT_LOOP 1000000
  26
  27 #define NUM_RX_BDS 4
  28 #define NUM_TX_BDS 4
  29 #define MAX_TX_SPACE 256
  30 #define I2C_RXTX_LEN 128        /* maximum tx/rx buffer length */
  31
  32 typedef struct I2C_BD {
  33         unsigned short status;
  34         unsigned short length;
  35         unsigned char *addr;
  36 } I2C_BD;
  37
  38 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
  39
  40 #define BD_I2C_TX_CL    0x0001  /* collision error */
  41 #define BD_I2C_TX_UN    0x0002  /* underflow error */
  42 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
  43 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
  44
  45 #define BD_I2C_RX_ERR   BD_SC_OV
  46
  47 typedef void (*i2c_ecb_t) (int, int);   /* error callback function */
  48
  49 /* This structure keeps track of the bd and buffer space usage. */
  50 typedef struct i2c_state {
  51         int rx_idx;             /* index   to next free Rx BD */
  52         int tx_idx;             /* index   to next free Tx BD */
  53         void *rxbd;             /* pointer to next free Rx BD */
  54         void *txbd;             /* pointer to next free Tx BD */
  55         int tx_space;           /* number  of Tx bytes left   */
  56         unsigned char *tx_buf;  /* pointer to free Tx area    */
  57         i2c_ecb_t err_cb;       /* error callback function    */
  58 } i2c_state_t;
  59
  60
  61 /* flags for i2c_send() and i2c_receive() */
  62 #define I2CF_ENABLE_SECONDARY   0x01  /* secondary_address is valid           */
  63 #define I2CF_START_COND         0x02  /* tx: generate start condition         */
  64 #define I2CF_STOP_COND          0x04  /* tx: generate stop  condition         */
  65
  66 /* return codes */
  67 #define I2CERR_NO_BUFFERS       0x01  /* no more BDs or buffer space          */
  68 #define I2CERR_MSG_TOO_LONG     0x02  /* tried to send/receive to much data   */
  69 #define I2CERR_TIMEOUT          0x03  /* timeout in i2c_doio()                */
  70 #define I2CERR_QUEUE_EMPTY      0x04  /* i2c_doio called without send/receive */
  71
  72 /* error callback flags */
  73 #define I2CECB_RX_ERR           0x10  /* this is a receive error              */
  74 #define     I2CECB_RX_ERR_OV    0x02  /* receive overrun error                */
  75 #define     I2CECB_RX_MASK      0x0f  /* mask for error bits                  */
  76 #define I2CECB_TX_ERR           0x20  /* this is a transmit error             */
  77 #define     I2CECB_TX_CL        0x01  /* transmit collision error             */
  78 #define     I2CECB_TX_UN        0x02  /* transmit underflow error             */
  79 #define     I2CECB_TX_NAK       0x04  /* transmit no ack error                */
  80 #define     I2CECB_TX_MASK      0x0f  /* mask for error bits                  */
  81 #define I2CECB_TIMEOUT          0x40  /* this is a timeout error              */
  82
  83 /*
  84  * Returns the best value of I2BRG to meet desired clock speed of I2C with
  85  * input parameters (clock speed, filter, and predivider value).
  86  * It returns computer speed value and the difference between it and desired
  87  * speed.
  88  */
  89 static inline int
  90 i2c_roundrate(int hz, int speed, int filter, int modval,
  91               int *brgval, int *totspeed)
  92 {
  93         int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
  94
  95         debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
  96                 hz, speed, filter, modval);
  97
  98         div = moddiv * speed;
  99         brgdiv = (hz + div - 1) / div;
 100
 101         debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
 102
 103         *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
 104
 105         if ((*brgval < 0) || (*brgval > 255)) {
 106                 debug("\t\trejected brgval=%d\n", *brgval);
 107                 return -1;
 108         }
 109
 110         brgdiv = 2 * (*brgval + 3 + (2 * filter));
 111         div = moddiv * brgdiv;
 112         *totspeed = hz / div;
 113
 114         debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
 115
 116         return 0;
 117 }
 118
 119 /*
 120  * Sets the I2C clock predivider and divider to meet required clock speed.
 121  */
 122 static int i2c_setrate(int hz, int speed)
 123 {
 124         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 125         volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
 126         int     brgval,
 127                 modval, /* 0-3 */
 128                 bestspeed_diff = speed,
 129                 bestspeed_brgval = 0,
 130                 bestspeed_modval = 0,
 131                 bestspeed_filter = 0,
 132                 totspeed,
 133                 filter = 0;     /* Use this fixed value */
 134
 135         for (modval = 0; modval < 4; modval++) {
 136                 if (i2c_roundrate
 137                     (hz, speed, filter, modval, &brgval, &totspeed) == 0) {
 138                         int diff = speed - totspeed;
 139
 140                         if ((diff >= 0) && (diff < bestspeed_diff)) {
 141                                 bestspeed_diff = diff;
 142                                 bestspeed_modval = modval;
 143                                 bestspeed_brgval = brgval;
 144                                 bestspeed_filter = filter;
 145                         }
 146                 }
 147         }
 148
 149         debug("[I2C] Best is:\n");
 150         debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 151                 hz,
 152                 speed,
 153                 bestspeed_filter,
 154                 bestspeed_modval,
 155                 bestspeed_brgval,
 156                 bestspeed_diff);
 157
 158         i2c->i2c_i2mod |=
 159                 ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
 160         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 161
 162         debug("[I2C] i2mod=%08x i2brg=%08x\n",
 163                 i2c->i2c_i2mod,
 164                 i2c->i2c_i2brg);
 165
 166         return 1;
 167 }
 168
 169 void i2c_init(int speed, int slaveaddr)
 170 {
 171         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 172         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 173         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 174         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 175         ulong rbase, tbase;
 176         volatile I2C_BD *rxbd, *txbd;
 177         uint dpaddr;
 178
 179 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 180         /* call board specific i2c bus reset routine before accessing the   */
 181         /* environment, which might be in a chip on that bus. For details   */
 182         /* about this problem see doc/I2C_Edge_Conditions.                  */
 183         i2c_init_board();
 184 #endif
 185
 186 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 187         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 188 #else
 189         /* Disable relocation */
 190         iip->iic_rpbase = 0;
 191 #endif
 192
 193 #ifdef CONFIG_SYS_ALLOC_DPRAM
 194         dpaddr = iip->iic_rbase;
 195         if (dpaddr == 0) {
 196                 /* need to allocate dual port ram */
 197                 dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
 198                                            (NUM_TX_BDS * sizeof(I2C_BD)) +
 199                                            MAX_TX_SPACE, 8);
 200         }
 201 #else
 202         dpaddr = CPM_I2C_BASE;
 203 #endif
 204
 205         /*
 206          * initialise data in dual port ram:
 207          *
 208          * dpaddr->rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 209          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 210          *                  tx buffer     (MAX_TX_SPACE bytes)
 211          */
 212
 213         rbase = dpaddr;
 214         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 215
 216         /* Initialize Port B I2C pins. */
 217         cp->cp_pbpar |= 0x00000030;
 218         cp->cp_pbdir |= 0x00000030;
 219         cp->cp_pbodr |= 0x00000030;
 220
 221         /* Disable interrupts */
 222         i2c->i2c_i2mod = 0x00;
 223         i2c->i2c_i2cmr = 0x00;
 224         i2c->i2c_i2cer = 0xff;
 225         i2c->i2c_i2add = slaveaddr;
 226
 227         /*
 228          * Set the I2C BRG Clock division factor from desired i2c rate
 229          * and current CPU rate (we assume sccr dfbgr field is 0;
 230          * divide BRGCLK by 1)
 231          */
 232         debug("[I2C] Setting rate...\n");
 233         i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
 234
 235         /* Set I2C controller in master mode */
 236         i2c->i2c_i2com = 0x01;
 237
 238         /* Set SDMA bus arbitration level to 5 (SDCR) */
 239         immap->im_siu_conf.sc_sdcr = 0x0001;
 240
 241         /* Initialize Tx/Rx parameters */
 242         iip->iic_rbase = rbase;
 243         iip->iic_tbase = tbase;
 244         rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
 245         txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
 246
 247         debug("[I2C] rbase = %04x\n", iip->iic_rbase);
 248         debug("[I2C] tbase = %04x\n", iip->iic_tbase);
 249         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 250         debug("[I2C] txbd = %08x\n", (int)txbd);
 251
 252         /* Set big endian byte order */
 253         iip->iic_tfcr = 0x10;
 254         iip->iic_rfcr = 0x10;
 255
 256         /* Set maximum receive size. */
 257         iip->iic_mrblr = I2C_RXTX_LEN;
 258
 259 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 260         /*
 261          *  Initialize required parameters if using microcode patch.
 262          */
 263         iip->iic_rbptr = iip->iic_rbase;
 264         iip->iic_tbptr = iip->iic_tbase;
 265         iip->iic_rstate = 0;
 266         iip->iic_tstate = 0;
 267 #else
 268         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 269         do {
 270                 __asm__ __volatile__("eieio");
 271         } while (cp->cp_cpcr & CPM_CR_FLG);
 272 #endif
 273
 274         /* Clear events and interrupts */
 275         i2c->i2c_i2cer = 0xff;
 276         i2c->i2c_i2cmr = 0x00;
 277 }
 278
 279 static void i2c_newio(i2c_state_t *state)
 280 {
 281         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 282         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 283         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 284
 285         debug("[I2C] i2c_newio\n");
 286
 287 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 288         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 289 #endif
 290         state->rx_idx = 0;
 291         state->tx_idx = 0;
 292         state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
 293         state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
 294         state->tx_space = MAX_TX_SPACE;
 295         state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 296         state->err_cb = NULL;
 297
 298         debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
 299         debug("[I2C] txbd = %08x\n", (int)state->txbd);
 300         debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
 301
 302         /* clear the buffer memory */
 303         memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
 304 }
 305
 306 static int
 307 i2c_send(i2c_state_t *state,
 308          unsigned char address,
 309          unsigned char secondary_address,
 310          unsigned int flags, unsigned short size, unsigned char *dataout)
 311 {
 312         volatile I2C_BD *txbd;
 313         int i, j;
 314
 315         debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 316                 address, secondary_address, flags, size);
 317
 318         /* trying to send message larger than BD */
 319         if (size > I2C_RXTX_LEN)
 320                 return I2CERR_MSG_TOO_LONG;
 321
 322         /* no more free bds */
 323         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 324                 return I2CERR_NO_BUFFERS;
 325
 326         txbd = (I2C_BD *) state->txbd;
 327         txbd->addr = state->tx_buf;
 328
 329         debug("[I2C] txbd = %08x\n", (int)txbd);
 330
 331         if (flags & I2CF_START_COND) {
 332                 debug("[I2C] Formatting addresses...\n");
 333                 if (flags & I2CF_ENABLE_SECONDARY) {
 334                         /* Length of msg + dest addr */
 335                         txbd->length = size + 2;
 336
 337                         txbd->addr[0] = address << 1;
 338                         txbd->addr[1] = secondary_address;
 339                         i = 2;
 340                 } else {
 341                         /* Length of msg + dest addr */
 342                         txbd->length = size + 1;
 343                         /* Write dest addr to BD */
 344                         txbd->addr[0] = address << 1;
 345                         i = 1;
 346                 }
 347         } else {
 348                 txbd->length = size;    /* Length of message */
 349                 i = 0;
 350         }
 351
 352         /* set up txbd */
 353         txbd->status = BD_SC_READY;
 354         if (flags & I2CF_START_COND)
 355                 txbd->status |= BD_I2C_TX_START;
 356         if (flags & I2CF_STOP_COND)
 357                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 358
 359         /* Copy data to send into buffer */
 360         debug("[I2C] copy data...\n");
 361         for(j = 0; j < size; i++, j++)
 362                 txbd->addr[i] = dataout[j];
 363
 364         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 365                 txbd->length,
 366                 txbd->status,
 367                 txbd->addr[0],
 368                 txbd->addr[1]);
 369
 370         /* advance state */
 371         state->tx_buf += txbd->length;
 372         state->tx_space -= txbd->length;
 373         state->tx_idx++;
 374         state->txbd = (void *) (txbd + 1);
 375
 376         return 0;
 377 }
 378
 379 static int
 380 i2c_receive(i2c_state_t *state,
 381             unsigned char address,
 382             unsigned char secondary_address,
 383             unsigned int flags,
 384             unsigned short size_to_expect, unsigned char *datain)
 385 {
 386         volatile I2C_BD *rxbd, *txbd;
 387
 388         debug("[I2C] i2c_receive %02d %02d %02d\n",
 389                 address, secondary_address, flags);
 390
 391         /* Expected to receive too much */
 392         if (size_to_expect > I2C_RXTX_LEN)
 393                 return I2CERR_MSG_TOO_LONG;
 394
 395         /* no more free bds */
 396         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 397             || state->tx_space < 2)
 398                 return I2CERR_NO_BUFFERS;
 399
 400         rxbd = (I2C_BD *) state->rxbd;
 401         txbd = (I2C_BD *) state->txbd;
 402
 403         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 404         debug("[I2C] txbd = %08x\n", (int)txbd);
 405
 406         txbd->addr = state->tx_buf;
 407
 408         /* set up TXBD for destination address */
 409         if (flags & I2CF_ENABLE_SECONDARY) {
 410                 txbd->length = 2;
 411                 txbd->addr[0] = address << 1;   /* Write data */
 412                 txbd->addr[1] = secondary_address;      /* Internal address */
 413                 txbd->status = BD_SC_READY;
 414         } else {
 415                 txbd->length = 1 + size_to_expect;
 416                 txbd->addr[0] = (address << 1) | 0x01;
 417                 txbd->status = BD_SC_READY;
 418                 memset(&txbd->addr[1], 0, txbd->length);
 419         }
 420
 421         /* set up rxbd for reception */
 422         rxbd->status = BD_SC_EMPTY;
 423         rxbd->length = size_to_expect;
 424         rxbd->addr = datain;
 425
 426         txbd->status |= BD_I2C_TX_START;
 427         if (flags & I2CF_STOP_COND) {
 428                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 429                 rxbd->status |= BD_SC_WRAP;
 430         }
 431
 432         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 433                 txbd->length,
 434                 txbd->status,
 435                 txbd->addr[0],
 436                 txbd->addr[1]);
 437         debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 438                 rxbd->length,
 439                 rxbd->status,
 440                 rxbd->addr[0],
 441                 rxbd->addr[1]);
 442
 443         /* advance state */
 444         state->tx_buf += txbd->length;
 445         state->tx_space -= txbd->length;
 446         state->tx_idx++;
 447         state->txbd = (void *) (txbd + 1);
 448         state->rx_idx++;
 449         state->rxbd = (void *) (rxbd + 1);
 450
 451         return 0;
 452 }
 453
 454
 455 static int i2c_doio(i2c_state_t *state)
 456 {
 457         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 458         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 459         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 460         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 461         volatile I2C_BD *txbd, *rxbd;
 462         volatile int j = 0;
 463
 464         debug("[I2C] i2c_doio\n");
 465
 466 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 467         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 468 #endif
 469
 470         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 471                 debug("[I2C] No I/O is queued\n");
 472                 return I2CERR_QUEUE_EMPTY;
 473         }
 474
 475         iip->iic_rbptr = iip->iic_rbase;
 476         iip->iic_tbptr = iip->iic_tbase;
 477
 478         /* Enable I2C */
 479         debug("[I2C] Enabling I2C...\n");
 480         i2c->i2c_i2mod |= 0x01;
 481
 482         /* Begin transmission */
 483         i2c->i2c_i2com |= 0x80;
 484
 485         /* Loop until transmit & receive completed */
 486
 487         if (state->tx_idx > 0) {
 488                 txbd = ((I2C_BD*)state->txbd) - 1;
 489
 490                 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
 491                         (ulong)txbd);
 492
 493                 while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
 494                         if (ctrlc())
 495                                 return (-1);
 496
 497                         __asm__ __volatile__("eieio");
 498                 }
 499         }
 500
 501         if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
 502                 rxbd = ((I2C_BD*)state->rxbd) - 1;
 503
 504                 debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
 505                         (ulong)rxbd);
 506
 507                 while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
 508                         if (ctrlc())
 509                                 return (-1);
 510
 511                         __asm__ __volatile__("eieio");
 512                 }
 513         }
 514
 515         /* Turn off I2C */
 516         i2c->i2c_i2mod &= ~0x01;
 517
 518         if (state->err_cb != NULL) {
 519                 int n, i, b;
 520
 521                 /*
 522                  * if we have an error callback function, look at the
 523                  * error bits in the bd status and pass them back
 524                  */
 525
 526                 if ((n = state->tx_idx) > 0) {
 527                         for (i = 0; i < n; i++) {
 528                                 txbd = ((I2C_BD *) state->txbd) - (n - i);
 529                                 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
 530                                         (*state->err_cb) (I2CECB_TX_ERR | b,
 531                                                           i);
 532                         }
 533                 }
 534
 535                 if ((n = state->rx_idx) > 0) {
 536                         for (i = 0; i < n; i++) {
 537                                 rxbd = ((I2C_BD *) state->rxbd) - (n - i);
 538                                 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
 539                                         (*state->err_cb) (I2CECB_RX_ERR | b,
 540                                                           i);
 541                         }
 542                 }
 543
 544                 if (j >= TOUT_LOOP)
 545                         (*state->err_cb) (I2CECB_TIMEOUT, 0);
 546         }
 547
 548         return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
 549 }
 550
 551 static int had_tx_nak;
 552
 553 static void i2c_test_callback(int flags, int xnum)
 554 {
 555         if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
 556                 had_tx_nak = 1;
 557 }
 558
 559 int i2c_probe(uchar chip)
 560 {
 561         i2c_state_t state;
 562         int rc;
 563         uchar buf[1];
 564
 565         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 566
 567         i2c_newio(&state);
 568
 569         state.err_cb = i2c_test_callback;
 570         had_tx_nak = 0;
 571
 572         rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
 573                          buf);
 574
 575         if (rc != 0)
 576                 return (rc);
 577
 578         rc = i2c_doio(&state);
 579
 580         if ((rc != 0) && (rc != I2CERR_TIMEOUT))
 581                 return (rc);
 582
 583         return (had_tx_nak);
 584 }
 585
 586 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 587 {
 588         i2c_state_t state;
 589         uchar xaddr[4];
 590         int rc;
 591
 592         xaddr[0] = (addr >> 24) & 0xFF;
 593         xaddr[1] = (addr >> 16) & 0xFF;
 594         xaddr[2] = (addr >> 8) & 0xFF;
 595         xaddr[3] = addr & 0xFF;
 596
 597 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 598         /*
 599          * EEPROM chips that implement "address overflow" are ones like
 600          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 601          * extra bits end up in the "chip address" bit slots.  This makes
 602          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 603          *
 604          * Note that we consider the length of the address field to still
 605          * be one byte because the extra address bits are hidden in the
 606          * chip address.
 607          */
 608         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 609 #endif
 610
 611         i2c_newio(&state);
 612
 613         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 614                       &xaddr[4 - alen]);
 615         if (rc != 0) {
 616                 printf("i2c_read: i2c_send failed (%d)\n", rc);
 617                 return 1;
 618         }
 619
 620         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 621         if (rc != 0) {
 622                 printf("i2c_read: i2c_receive failed (%d)\n", rc);
 623                 return 1;
 624         }
 625
 626         rc = i2c_doio(&state);
 627         if (rc != 0) {
 628                 printf("i2c_read: i2c_doio failed (%d)\n", rc);
 629                 return 1;
 630         }
 631         return 0;
 632 }
 633
 634 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 635 {
 636         i2c_state_t state;
 637         uchar xaddr[4];
 638         int rc;
 639
 640         xaddr[0] = (addr >> 24) & 0xFF;
 641         xaddr[1] = (addr >> 16) & 0xFF;
 642         xaddr[2] = (addr >> 8) & 0xFF;
 643         xaddr[3] = addr & 0xFF;
 644
 645 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 646         /*
 647          * EEPROM chips that implement "address overflow" are ones like
 648          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 649          * extra bits end up in the "chip address" bit slots.  This makes
 650          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 651          *
 652          * Note that we consider the length of the address field to still
 653          * be one byte because the extra address bits are hidden in the
 654          * chip address.
 655          */
 656         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 657 #endif
 658
 659         i2c_newio(&state);
 660
 661         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 662                       &xaddr[4 - alen]);
 663         if (rc != 0) {
 664                 printf("i2c_write: first i2c_send failed (%d)\n", rc);
 665                 return 1;
 666         }
 667
 668         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 669         if (rc != 0) {
 670                 printf("i2c_write: second i2c_send failed (%d)\n", rc);
 671                 return 1;
 672         }
 673
 674         rc = i2c_doio(&state);
 675         if (rc != 0) {
 676                 printf("i2c_write: i2c_doio failed (%d)\n", rc);
 677                 return 1;
 678         }
 679         return 0;
 680 }
 681
 682 #endif /* CONFIG_HARD_I2C */