3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
14 DECLARE_GLOBAL_DATA_PTR;
18 #if defined(CONFIG_CMD_NET) && \
19 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
21 /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
22 #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
23 #define CONFIG_ETHER_ON_FEC1 1
26 /* define WANT_MII when MII support is required */
27 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
36 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
37 #error "CONFIG_MII has to be defined!"
42 #if defined(CONFIG_RMII) && !defined(WANT_MII)
43 #error RMII support is unusable without a working PHY.
46 #ifdef CONFIG_SYS_DISCOVER_PHY
47 static int mii_discover_phy(struct eth_device *dev);
50 int fec8xx_miiphy_read(const char *devname, unsigned char addr,
51 unsigned char reg, unsigned short *value);
52 int fec8xx_miiphy_write(const char *devname, unsigned char addr,
53 unsigned char reg, unsigned short value);
55 static struct ether_fcc_info_s
64 #if defined(CONFIG_ETHER_ON_FEC1)
67 offsetof(immap_t, im_cpm.cp_fec1),
68 #if defined(CONFIG_FEC1_PHY)
78 #if defined(CONFIG_ETHER_ON_FEC2)
81 offsetof(immap_t, im_cpm.cp_fec2),
82 #if defined(CONFIG_FEC2_PHY)
93 /* Ethernet Transmit and Receive Buffers */
94 #define DBUF_LENGTH 1520
100 #define PKT_MAXBUF_SIZE 1518
101 #define PKT_MINBUF_SIZE 64
102 #define PKT_MAXBLR_SIZE 1520
105 static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
107 #error txbuf must be aligned.
110 static uint rxIdx; /* index of the current RX buffer */
111 static uint txIdx; /* index of the current TX buffer */
114 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
115 * immr->udata_bd address on Dual-Port RAM
116 * Provide for Double Buffering
119 typedef volatile struct CommonBufferDescriptor {
120 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
121 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
124 static RTXBD *rtx = NULL;
126 static int fec_send(struct eth_device *dev, void *packet, int length);
127 static int fec_recv(struct eth_device* dev);
128 static int fec_init(struct eth_device* dev, bd_t * bd);
129 static void fec_halt(struct eth_device* dev);
130 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
131 static void __mii_init(void);
134 int fec_initialize(bd_t *bis)
136 struct eth_device* dev;
137 struct ether_fcc_info_s *efis;
140 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
142 dev = malloc(sizeof(*dev));
146 memset(dev, 0, sizeof(*dev));
148 /* for FEC1 make sure that the name of the interface is the same
149 as the old one for compatibility reasons */
151 sprintf (dev->name, "FEC");
153 sprintf (dev->name, "FEC%d",
154 ether_fcc_info[i].ether_index + 1);
157 efis = ðer_fcc_info[i];
160 * reset actual phy addr
162 efis->actual_phy_addr = -1;
165 dev->init = fec_init;
166 dev->halt = fec_halt;
167 dev->send = fec_send;
168 dev->recv = fec_recv;
172 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
173 miiphy_register(dev->name,
174 fec8xx_miiphy_read, fec8xx_miiphy_write);
180 static int fec_send(struct eth_device *dev, void *packet, int length)
183 struct ether_fcc_info_s *efis = dev->priv;
184 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
190 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
195 printf("TX not ready\n");
198 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
199 rtx->txbd[txIdx].cbd_datlen = length;
200 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
203 /* Activate transmit Buffer Descriptor polling */
204 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
207 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
208 #if defined(CONFIG_ICU862)
216 printf("TX timeout\n");
219 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
220 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
221 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
223 /* return only status bits */;
224 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
226 txIdx = (txIdx + 1) % TX_BUF_CNT;
231 static int fec_recv (struct eth_device *dev)
233 struct ether_fcc_info_s *efis = dev->priv;
234 volatile fec_t *fecp =
235 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
239 /* section 16.9.23.2 */
240 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
242 break; /* nothing received - leave for() loop */
245 length = rtx->rxbd[rxIdx].cbd_datlen;
247 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
249 printf ("%s[%d] err: %x\n",
250 __FUNCTION__, __LINE__,
251 rtx->rxbd[rxIdx].cbd_sc);
254 uchar *rx = NetRxPackets[rxIdx];
258 #if defined(CONFIG_CMD_CDP)
260 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
261 && !is_cdp_packet((uchar *)rx))
265 * Pass the packet up to the protocol layers.
268 NetReceive (rx, length);
271 /* Give the buffer back to the FEC. */
272 rtx->rxbd[rxIdx].cbd_datlen = 0;
274 /* wrap around buffer index when necessary */
275 if ((rxIdx + 1) >= PKTBUFSRX) {
276 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
277 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
280 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
286 /* Try to fill Buffer Descriptors */
287 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
293 /**************************************************************
295 * FEC Ethernet Initialization Routine
297 *************************************************************/
299 #define FEC_ECNTRL_PINMUX 0x00000004
300 #define FEC_ECNTRL_ETHER_EN 0x00000002
301 #define FEC_ECNTRL_RESET 0x00000001
303 #define FEC_RCNTRL_BC_REJ 0x00000010
304 #define FEC_RCNTRL_PROM 0x00000008
305 #define FEC_RCNTRL_MII_MODE 0x00000004
306 #define FEC_RCNTRL_DRT 0x00000002
307 #define FEC_RCNTRL_LOOP 0x00000001
309 #define FEC_TCNTRL_FDEN 0x00000004
310 #define FEC_TCNTRL_HBC 0x00000002
311 #define FEC_TCNTRL_GTS 0x00000001
313 #define FEC_RESET_DELAY 50
315 #if defined(CONFIG_RMII)
317 static inline void fec_10Mbps(struct eth_device *dev)
319 struct ether_fcc_info_s *efis = dev->priv;
320 int fecidx = efis->ether_index;
321 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
323 if ((unsigned int)fecidx >= 2)
326 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
329 static inline void fec_100Mbps(struct eth_device *dev)
331 struct ether_fcc_info_s *efis = dev->priv;
332 int fecidx = efis->ether_index;
333 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
335 if ((unsigned int)fecidx >= 2)
338 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
343 static inline void fec_full_duplex(struct eth_device *dev)
345 struct ether_fcc_info_s *efis = dev->priv;
346 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
348 fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
349 fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
352 static inline void fec_half_duplex(struct eth_device *dev)
354 struct ether_fcc_info_s *efis = dev->priv;
355 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
357 fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
358 fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
361 static void fec_pin_init(int fecidx)
364 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
367 * Set MII speed to 2.5 MHz or slightly below.
369 * According to the MPC860T (Rev. D) Fast ethernet controller user
371 * the MII management interface clock must be less than or equal
373 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
374 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
376 * All MII configuration is done via FEC1 registers:
378 immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
380 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
381 /* use MDC for MII */
382 immr->im_ioport.iop_pdpar |= 0x0080;
383 immr->im_ioport.iop_pddir &= ~0x0080;
387 #if defined(CONFIG_ETHER_ON_FEC1)
389 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
391 #if !defined(CONFIG_RMII)
393 immr->im_ioport.iop_papar |= 0xf830;
394 immr->im_ioport.iop_padir |= 0x0830;
395 immr->im_ioport.iop_padir &= ~0xf000;
397 immr->im_cpm.cp_pbpar |= 0x00001001;
398 immr->im_cpm.cp_pbdir &= ~0x00001001;
400 immr->im_ioport.iop_pcpar |= 0x000c;
401 immr->im_ioport.iop_pcdir &= ~0x000c;
403 immr->im_cpm.cp_pepar |= 0x00000003;
404 immr->im_cpm.cp_pedir |= 0x00000003;
405 immr->im_cpm.cp_peso &= ~0x00000003;
407 immr->im_cpm.cp_cptr &= ~0x00000100;
411 #if !defined(CONFIG_FEC1_PHY_NORXERR)
412 immr->im_ioport.iop_papar |= 0x1000;
413 immr->im_ioport.iop_padir &= ~0x1000;
415 immr->im_ioport.iop_papar |= 0xe810;
416 immr->im_ioport.iop_padir |= 0x0810;
417 immr->im_ioport.iop_padir &= ~0xe000;
419 immr->im_cpm.cp_pbpar |= 0x00000001;
420 immr->im_cpm.cp_pbdir &= ~0x00000001;
422 immr->im_cpm.cp_cptr |= 0x00000100;
423 immr->im_cpm.cp_cptr &= ~0x00000050;
425 #endif /* !CONFIG_RMII */
427 #elif !defined(CONFIG_ICU862)
429 * Configure all of port D for MII.
431 immr->im_ioport.iop_pdpar = 0x1fff;
434 * Bits moved from Rev. D onward
436 if ((get_immr(0) & 0xffff) < 0x0501)
437 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
439 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
442 * Configure port A for MII.
445 #if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY)
448 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
449 * * of CPU, so for this board we need to configure Utopia and
450 * * enable PD8 to MII-MDC function
452 immr->im_ioport.iop_pdpar |= 0x4080;
456 * Has Utopia been configured?
458 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
460 * YES - Use MUXED mode for UTOPIA bus.
461 * This frees Port A for use by MII (see 862UM table 41-6).
463 immr->im_ioport.utmode &= ~0x80;
466 * NO - set SPLIT mode for UTOPIA bus.
468 * This doesn't really effect UTOPIA (which isn't
469 * enabled anyway) but just tells the 862
470 * to use port A for MII (see 862UM table 41-6).
472 immr->im_ioport.utmode |= 0x80;
474 #endif /* !defined(CONFIG_ICU862) */
476 #endif /* CONFIG_ETHER_ON_FEC1 */
477 } else if (fecidx == 1) {
479 #if defined(CONFIG_ETHER_ON_FEC2)
481 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
483 #if !defined(CONFIG_RMII)
484 immr->im_cpm.cp_pepar |= 0x0003fffc;
485 immr->im_cpm.cp_pedir |= 0x0003fffc;
486 immr->im_cpm.cp_peso &= ~0x000087fc;
487 immr->im_cpm.cp_peso |= 0x00037800;
489 immr->im_cpm.cp_cptr &= ~0x00000080;
492 #if !defined(CONFIG_FEC2_PHY_NORXERR)
493 immr->im_cpm.cp_pepar |= 0x00000010;
494 immr->im_cpm.cp_pedir |= 0x00000010;
495 immr->im_cpm.cp_peso &= ~0x00000010;
497 immr->im_cpm.cp_pepar |= 0x00039620;
498 immr->im_cpm.cp_pedir |= 0x00039620;
499 immr->im_cpm.cp_peso |= 0x00031000;
500 immr->im_cpm.cp_peso &= ~0x00008620;
502 immr->im_cpm.cp_cptr |= 0x00000080;
503 immr->im_cpm.cp_cptr &= ~0x00000028;
504 #endif /* CONFIG_RMII */
506 #endif /* CONFIG_MPC885_FAMILY */
508 #endif /* CONFIG_ETHER_ON_FEC2 */
513 static int fec_reset(volatile fec_t *fecp)
518 * A delay is required between a reset of the FEC block and
519 * initialization of other FEC registers because the reset takes
520 * some time to complete. If you don't delay, subsequent writes
521 * to FEC registers might get killed by the reset routine which is
525 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
527 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
531 if (i == FEC_RESET_DELAY)
537 static int fec_init (struct eth_device *dev, bd_t * bd)
539 struct ether_fcc_info_s *efis = dev->priv;
540 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
541 volatile fec_t *fecp =
542 (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
545 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
546 /* the MII interface is connected to FEC1
547 * so for the miiphy_xxx function to work we must
548 * call mii_init since fec_halt messes the thing up
550 if (efis->ether_index != 0)
554 if (fec_reset(fecp) < 0)
555 printf ("FEC_RESET_DELAY timeout\n");
557 /* We use strictly polling mode only
561 /* Clear any pending interrupt
563 fecp->fec_ievent = 0xffc0;
565 /* No need to set the IVEC register */
567 /* Set station address
569 #define ea dev->enetaddr
570 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
571 fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
574 #if defined(CONFIG_CMD_CDP)
576 * Turn on multicast address hash table
578 fecp->fec_hash_table_high = 0xffffffff;
579 fecp->fec_hash_table_low = 0xffffffff;
581 /* Clear multicast address hash table
583 fecp->fec_hash_table_high = 0;
584 fecp->fec_hash_table_low = 0;
587 /* Set maximum receive buffer size.
589 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
591 /* Set maximum frame length
593 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
596 * Setup Buffers and Buffer Desriptors
602 #ifdef CONFIG_SYS_ALLOC_DPRAM
603 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
604 dpram_alloc_align (sizeof (RTXBD), 8));
606 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
610 * Setup Receiver Buffer Descriptors (13.14.24.18)
614 for (i = 0; i < PKTBUFSRX; i++) {
615 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
616 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
617 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
619 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
622 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
626 for (i = 0; i < TX_BUF_CNT; i++) {
627 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
628 rtx->txbd[i].cbd_datlen = 0; /* Reset */
629 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
631 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
633 /* Set receive and transmit descriptor base
635 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
636 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
640 #if 0 /* Full duplex mode */
641 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
642 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
643 #else /* Half duplex mode */
644 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
645 fecp->fec_x_cntrl = 0;
648 /* Enable big endian and don't care about SDMA FC.
650 fecp->fec_fun_code = 0x78000000;
653 * Setup the pin configuration of the FEC
655 fec_pin_init (efis->ether_index);
661 * Now enable the transmit and receive processing
663 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
665 if (efis->phy_addr == -1) {
666 #ifdef CONFIG_SYS_DISCOVER_PHY
668 * wait for the PHY to wake up after reset
670 efis->actual_phy_addr = mii_discover_phy (dev);
672 if (efis->actual_phy_addr == -1) {
673 printf ("Unable to discover phy!\n");
677 efis->actual_phy_addr = -1;
680 efis->actual_phy_addr = efis->phy_addr;
683 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
685 * adapt the RMII speed to the speed of the phy
687 if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
694 #if defined(CONFIG_MII)
696 * adapt to the half/full speed settings
698 if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
699 fec_full_duplex (dev);
701 fec_half_duplex (dev);
705 /* And last, try to fill Rx Buffer Descriptors */
706 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
708 efis->initialized = 1;
714 static void fec_halt(struct eth_device* dev)
716 struct ether_fcc_info_s *efis = dev->priv;
717 volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
720 /* avoid halt if initialized; mii gets stuck otherwise */
721 if (!efis->initialized)
725 * A delay is required between a reset of the FEC block and
726 * initialization of other FEC registers because the reset takes
727 * some time to complete. If you don't delay, subsequent writes
728 * to FEC registers might get killed by the reset routine which is
732 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
734 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
738 if (i == FEC_RESET_DELAY) {
739 printf ("FEC_RESET_DELAY timeout\n");
743 efis->initialized = 0;
746 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
748 /* Make MII read/write commands for the FEC.
751 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
754 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
755 (REG & 0x1f) << 18) | \
758 /* Interrupt events/masks.
760 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
761 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
762 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
763 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
764 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
765 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
766 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
767 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
768 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
769 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
771 /* PHY identification
773 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
774 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
775 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
776 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
777 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
778 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
779 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
780 #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
781 #define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
783 /* send command to phy using mii, wait for result */
785 mii_send(uint mii_cmd)
791 ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
793 ep->fec_mii_data = mii_cmd; /* command to phy */
795 /* wait for mii complete */
797 while (!(ep->fec_ievent & FEC_ENET_MII)) {
799 printf("mii_send STUCK!\n");
803 mii_reply = ep->fec_mii_data; /* result from phy */
804 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
806 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
807 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
809 return (mii_reply & 0xffff); /* data read from phy */
813 #if defined(CONFIG_SYS_DISCOVER_PHY)
814 static int mii_discover_phy(struct eth_device *dev)
816 #define MAX_PHY_PASSES 11
822 phyaddr = -1; /* didn't find a PHY yet */
823 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
825 /* PHY may need more time to recover from reset.
826 * The LXT970 needs 50ms typical, no maximum is
827 * specified, so wait 10ms before try again.
828 * With 11 passes this gives it 100ms to wake up.
830 udelay(10000); /* wait 10ms */
832 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
833 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
835 printf("PHY type 0x%x pass %d type ", phytype, pass);
837 if (phytype != 0xffff) {
839 phytype |= mii_send(mk_mii_read(phyno,
843 printf("PHY @ 0x%x pass %d type ",phyno,pass);
844 switch (phytype & 0xfffffff0) {
857 case PHY_ID_AMD79C784:
858 printf("AMD79C784\n");
860 case PHY_ID_LSI80225B:
861 printf("LSI L80225/B\n");
864 printf("Davicom DM9161\n");
866 case PHY_ID_KSM8995M:
867 printf("MICREL KS8995M\n");
870 printf("0x%08x\n", phytype);
878 printf("No PHY device found.\n");
882 #endif /* CONFIG_SYS_DISCOVER_PHY */
884 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
886 /****************************************************************************
887 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
888 * This function is a subset of eth_init
889 ****************************************************************************
891 static void __mii_init(void)
893 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
894 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
896 if (fec_reset(fecp) < 0)
897 printf ("FEC_RESET_DELAY timeout\n");
899 /* We use strictly polling mode only
903 /* Clear any pending interrupt
905 fecp->fec_ievent = 0xffc0;
907 /* Now enable the transmit and receive processing
909 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
918 /* Setup the pin configuration of the FEC(s)
920 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
921 fec_pin_init(ether_fcc_info[i].ether_index);
924 /*****************************************************************************
925 * Read and write a MII PHY register, routines used by MII Utilities
927 * FIXME: These routines are expected to return 0 on success, but mii_send
928 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
929 * no PHY connected...
930 * For now always return 0.
931 * FIXME: These routines only work after calling eth_init() at least once!
932 * Otherwise they hang in mii_send() !!! Sorry!
933 *****************************************************************************/
935 int fec8xx_miiphy_read(const char *devname, unsigned char addr,
936 unsigned char reg, unsigned short *value)
938 short rdreg; /* register working value */
941 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
943 rdreg = mii_send(mk_mii_read(addr, reg));
947 printf ("0x%04x\n", *value);
952 int fec8xx_miiphy_write(const char *devname, unsigned char addr,
953 unsigned char reg, unsigned short value)
956 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
958 (void)mii_send(mk_mii_write(addr, reg, value));
961 printf ("0x%04x\n", value);