2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
14 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
15 DECLARE_GLOBAL_DATA_PTR;
18 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
19 defined(CONFIG_SYS_SMC_UCODE_PATCH)
20 void cpm_load_patch (volatile immap_t * immr);
24 * Breath some life into the CPU...
26 * Set up the memory map,
27 * initialize a bunch of registers,
28 * initialize the UPM's
30 void cpu_init_f (volatile immap_t * immr)
32 volatile memctl8xx_t *memctl = &immr->im_memctl;
33 # ifdef CONFIG_SYS_PLPRCR
38 /* SYPCR - contains watchdog control (11-9) */
40 immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
42 #if defined(CONFIG_WATCHDOG)
43 reset_8xx_watchdog (immr);
44 #endif /* CONFIG_WATCHDOG */
46 /* SIUMCR - contains debug pin configuration (11-6) */
47 immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
48 /* initialize timebase status and control register (11-26) */
51 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
52 immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
54 /* initialize the PIT (11-31) */
56 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
57 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
59 /* System integration timers. Don't change EBDF! (15-27) */
61 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
62 reg = immr->im_clkrst.car_sccr;
64 reg |= CONFIG_SYS_SCCR;
65 immr->im_clkrst.car_sccr = reg;
67 /* PLL (CPU clock) settings (15-30) */
69 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
71 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
72 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
73 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
76 * For newer (starting MPC866) chips PLPRCR layout is different.
78 #ifdef CONFIG_SYS_PLPRCR
79 if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
80 mfmask = PLPRCR_MFACT_MSK;
82 mfmask = PLPRCR_MF_MSK;
84 if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
85 reg = CONFIG_SYS_PLPRCR; /* reset control bits */
87 reg = immr->im_clkrst.car_plprcr;
88 reg &= mfmask; /* isolate MF-related fields */
89 reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
91 immr->im_clkrst.car_plprcr = reg;
98 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
99 reg = memctl->memc_br0;
100 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
101 reg |= BR_V; /* then add just the "Bank Valid" bit */
102 memctl->memc_br0 = reg;
104 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
105 * preliminary addresses - these have to be modified later
106 * when FLASH size has been determined
108 * Depending on the size of the memory region defined by
109 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
110 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
111 * map CONFIG_SYS_MONITOR_BASE.
113 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
114 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
116 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
117 * base address remains as 0x00000000. However, the address mask
118 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
121 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
122 * CONFIG_SYS_BR0_PRELIM in advance.
124 * [Thanks to Michael Liao for this explanation.
125 * I owe him a free beer. - wd]
128 #if defined(CONFIG_SYS_OR0_REMAP)
129 memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
131 #if defined(CONFIG_SYS_OR1_REMAP)
132 memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
134 #if defined(CONFIG_SYS_OR5_REMAP)
135 memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
138 /* now restrict to preliminary range */
139 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
140 memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
142 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
143 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
144 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
147 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
148 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
149 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
152 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
153 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
154 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
157 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
158 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
159 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
162 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
163 memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
164 memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
167 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
168 memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
169 memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
172 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
173 memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
174 memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
180 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
181 do { /* Spin until command processed */
183 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
185 #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
186 /* write config value */
187 immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
190 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
191 defined(CONFIG_SYS_SMC_UCODE_PATCH)
192 cpm_load_patch (immr); /* load mpc8xx microcode patch */
197 * initialize higher level parts of CPU like timers
199 int cpu_init_r (void)
201 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
203 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
206 #ifdef CONFIG_SYS_RTCSC
207 /* Unlock RTSC register */
208 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
209 /* write config value */
210 immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
213 #ifdef CONFIG_SYS_RMDS
214 /* write config value */
215 immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;