2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/cpm_8xx.h>
16 * Breath some life into the CPU...
18 * Set up the memory map,
19 * initialize a bunch of registers,
20 * initialize the UPM's
22 void cpu_init_f(immap_t __iomem *immr)
24 memctl8xx_t __iomem *memctl = &immr->im_memctl;
27 /* SYPCR - contains watchdog control (11-9) */
29 out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
31 #if defined(CONFIG_WATCHDOG)
32 reset_8xx_watchdog(immr);
33 #endif /* CONFIG_WATCHDOG */
35 /* SIUMCR - contains debug pin configuration (11-6) */
36 setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
37 /* initialize timebase status and control register (11-26) */
40 out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
41 out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR | TBSCR_TBE);
43 /* Unlock timebase register */
44 out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY);
46 /* initialize the PIT (11-31) */
48 out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
49 out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
51 /* System integration timers. Don't change EBDF! (15-27) */
53 out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
54 clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
58 * MPC866/885 ERRATA GLL2
60 * In 1:2:1 mode, when HRESET is detected at the positive edge of
61 * EXTCLK, then there will be a loss of phase between
66 * 1. Write 1'b00 to SCCR[EBDF].
67 * 2. Write 1'b01 to SCCR[EBDF].
68 * 3. Rewrite the desired value to the PLPRCR register.
70 reg = in_be32(&immr->im_clkrst.car_sccr);
71 /* Are we in mode 1:2:1 ? */
72 if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
73 clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
74 setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
77 /* PLL (CPU clock) settings (15-30) */
79 out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
81 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
82 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
83 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
86 * For newer (starting MPC866) chips PLPRCR layout is different.
88 #ifdef CONFIG_SYS_PLPRCR
89 if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
90 out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
91 else /* isolate MF-related fields and reset control bits */
92 clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
100 /* Clear everything except Port Size bits & add the "Bank Valid" bit */
101 clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
103 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
104 * preliminary addresses - these have to be modified later
105 * when FLASH size has been determined
107 * Depending on the size of the memory region defined by
108 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
109 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
110 * map CONFIG_SYS_MONITOR_BASE.
112 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
113 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
115 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
116 * base address remains as 0x00000000. However, the address mask
117 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
120 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
121 * CONFIG_SYS_BR0_PRELIM in advance.
123 * [Thanks to Michael Liao for this explanation.
124 * I owe him a free beer. - wd]
127 #if defined(CONFIG_SYS_OR0_REMAP)
128 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
130 #if defined(CONFIG_SYS_OR1_REMAP)
131 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
133 #if defined(CONFIG_SYS_OR5_REMAP)
134 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
137 /* now restrict to preliminary range */
138 out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
139 out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
141 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
142 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
143 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
146 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
147 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
148 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
151 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
152 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
153 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
156 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
157 out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
158 out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
161 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
162 out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
163 out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
166 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
167 out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
168 out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
171 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
172 out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
173 out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
179 out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
180 /* Spin until command processed */
181 while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
186 * initialize higher level parts of CPU like timers