2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
14 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
15 DECLARE_GLOBAL_DATA_PTR;
18 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
19 defined(CONFIG_SYS_SMC_UCODE_PATCH)
20 void cpm_load_patch (volatile immap_t * immr);
24 * Breath some life into the CPU...
26 * Set up the memory map,
27 * initialize a bunch of registers,
28 * initialize the UPM's
30 void cpu_init_f (volatile immap_t * immr)
33 volatile memctl8xx_t *memctl = &immr->im_memctl;
34 # ifdef CONFIG_SYS_PLPRCR
40 /* SYPCR - contains watchdog control (11-9) */
42 immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
44 #if defined(CONFIG_WATCHDOG)
45 reset_8xx_watchdog (immr);
46 #endif /* CONFIG_WATCHDOG */
48 /* SIUMCR - contains debug pin configuration (11-6) */
49 #ifndef CONFIG_SVM_SC8xx
50 immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
52 immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
54 /* initialize timebase status and control register (11-26) */
57 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
58 immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
60 /* initialize the PIT (11-31) */
62 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
63 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
65 /* System integration timers. Don't change EBDF! (15-27) */
67 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
68 reg = immr->im_clkrst.car_sccr;
70 reg |= CONFIG_SYS_SCCR;
71 immr->im_clkrst.car_sccr = reg;
73 /* PLL (CPU clock) settings (15-30) */
75 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
77 #ifndef CONFIG_MBX /* MBX board does things different */
79 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
80 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
81 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
84 * For newer (starting MPC866) chips PLPRCR layout is different.
86 #ifdef CONFIG_SYS_PLPRCR
87 if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
88 mfmask = PLPRCR_MFACT_MSK;
90 mfmask = PLPRCR_MF_MSK;
92 if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
93 reg = CONFIG_SYS_PLPRCR; /* reset control bits */
95 reg = immr->im_clkrst.car_plprcr;
96 reg &= mfmask; /* isolate MF-related fields */
97 reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
99 immr->im_clkrst.car_plprcr = reg;
106 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
107 reg = memctl->memc_br0;
108 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
109 reg |= BR_V; /* then add just the "Bank Valid" bit */
110 memctl->memc_br0 = reg;
112 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
113 * preliminary addresses - these have to be modified later
114 * when FLASH size has been determined
116 * Depending on the size of the memory region defined by
117 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
118 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
119 * map CONFIG_SYS_MONITOR_BASE.
121 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
122 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
124 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
125 * base address remains as 0x00000000. However, the address mask
126 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
129 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
130 * CONFIG_SYS_BR0_PRELIM in advance.
132 * [Thanks to Michael Liao for this explanation.
133 * I owe him a free beer. - wd]
136 #if defined(CONFIG_HERMES) || \
137 defined(CONFIG_ICU862) || \
138 defined(CONFIG_IP860) || \
139 defined(CONFIG_IVML24) || \
140 defined(CONFIG_IVMS8) || \
141 defined(CONFIG_LWMON) || \
142 defined(CONFIG_MHPC) || \
143 defined(CONFIG_R360MPI) || \
144 defined(CONFIG_RMU) || \
145 defined(CONFIG_RPXCLASSIC) || \
146 defined(CONFIG_RPXLITE) || \
147 defined(CONFIG_SPC1920) || \
148 defined(CONFIG_SPD823TS)
150 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
153 #if defined(CONFIG_SYS_OR0_REMAP)
154 memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
156 #if defined(CONFIG_SYS_OR1_REMAP)
157 memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
159 #if defined(CONFIG_SYS_OR5_REMAP)
160 memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
163 /* now restrict to preliminary range */
164 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
165 memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
167 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
168 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
169 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
172 #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
173 memctl->memc_br0 = 0;
176 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
177 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
178 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
181 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
182 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
183 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
186 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
187 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
188 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
191 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
192 memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
193 memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
196 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
197 memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
198 memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
201 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
202 memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
203 memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
206 #endif /* ! CONFIG_MBX */
211 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
212 do { /* Spin until command processed */
214 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
218 * on the MBX, things are a little bit different:
219 * - we need to read the VPD to get board information
220 * - the plprcr is set up dynamically
221 * - the memory controller is set up dynamically
224 #endif /* CONFIG_MBX */
226 #ifdef CONFIG_RPXCLASSIC
230 #if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
234 #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
235 /* write config value */
236 immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
239 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
240 defined(CONFIG_SYS_SMC_UCODE_PATCH)
241 cpm_load_patch (immr); /* load mpc8xx microcode patch */
246 * initialize higher level parts of CPU like timers
248 int cpu_init_r (void)
250 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
252 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
255 #ifdef CONFIG_SYS_RTCSC
256 /* Unlock RTSC register */
257 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
258 /* write config value */
259 immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
262 #ifdef CONFIG_SYS_RMDS
263 /* write config value */
264 immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;