2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
42 #include <asm/cache.h>
43 #include <linux/compiler.h>
46 #if defined(CONFIG_OF_LIBFDT)
48 #include <libfdt_env.h>
49 #include <fdt_support.h>
52 DECLARE_GLOBAL_DATA_PTR;
54 static char *cpu_warning = "\n " \
55 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
57 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
58 !defined(CONFIG_MPC862))
60 static int check_CPU (long clock, uint pvr, uint immr)
63 # if defined(CONFIG_MPC855)
65 # elif defined(CONFIG_MPC860P)
70 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
77 /* the highest 16 bits should be 0x0050 for a 860 */
79 if ((pvr >> 16) != 0x0050)
82 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
87 * Some boards use sockets so different CPUs can be used.
88 * We have to check chip version in run time.
91 case 0x00020001: pre = 'P'; break;
92 case 0x00030001: break;
93 case 0x00120003: suf = "A"; break;
94 case 0x00130003: suf = "A3"; break;
96 case 0x00200004: suf = "B"; break;
98 case 0x00300004: suf = "C"; break;
99 case 0x00310004: suf = "C1"; m = 1; break;
101 case 0x00200064: mid = "SR"; suf = "B"; break;
102 case 0x00300065: mid = "SR"; suf = "C"; break;
103 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
104 case 0x05010000: suf = "D3"; m = 1; break;
105 case 0x05020000: suf = "D4"; m = 1; break;
106 /* this value is not documented anywhere */
107 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
108 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
109 case 0x08010004: /* Rev. A.0 */
112 case 0x08000003: /* Rev. 0.3 */
116 # if defined(CONFIG_MPC852T)
118 # elif defined(CONFIG_MPC859T)
120 # elif defined(CONFIG_MPC859DSL)
122 # elif defined(CONFIG_MPC866T)
125 "PC866x"; /* Unknown chip from MPC866 family */
128 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
130 id_str = "PC885"; /* 870/875/880/885 */
133 default: suf = NULL; break;
137 id_str = "PC86x"; /* Unknown 86x chip */
139 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
141 printf ("unknown M%s (0x%08x)", id_str, k);
144 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
145 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
147 CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
148 ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
149 CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
150 ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
153 printf (" at %s MHz: ", strmhz (buf, clock));
155 printf ("%u kB I-Cache %u kB D-Cache",
156 checkicache () >> 10,
160 /* do we have a FEC (860T/P or 852/859/866/885)? */
162 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
163 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
164 printf (" FEC present");
174 if(clock != measure_gclk()) {
175 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
182 #elif defined(CONFIG_MPC862)
184 static int check_CPU (long clock, uint pvr, uint immr)
186 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
190 __maybe_unused char *mid = "xx";
193 /* the highest 16 bits should be 0x0050 for a 8xx */
195 if ((pvr >> 16) != 0x0050)
198 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
203 /* this value is not documented anywhere */
204 case 0x06000000: mid = "P"; suf = "0"; break;
205 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
206 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
207 default: suf = NULL; break;
210 #ifndef CONFIG_MPC857
212 printf ("%cPC862%sZPnn%s", pre, mid, suf);
214 printf ("unknown MPC862 (0x%08x)", k);
217 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
219 printf ("unknown MPC857 (0x%08x)", k);
222 printf (" at %s MHz:", strmhz (buf, clock));
224 printf (" %u kB I-Cache", checkicache () >> 10);
225 printf (" %u kB D-Cache", checkdcache () >> 10);
227 /* lets check and see if we're running on a 862T (or P?) */
229 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
230 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
231 printf (" FEC present");
243 #elif defined(CONFIG_MPC823)
245 static int check_CPU (long clock, uint pvr, uint immr)
247 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
252 /* the highest 16 bits should be 0x0050 for a 8xx */
254 if ((pvr >> 16) != 0x0050)
257 k = (immr << 16) | in_be16((ushort *)&immap->im_cpm.cp_dparam[0xB0]);
262 case 0x20000000: suf = "0"; break;
263 case 0x20010000: suf = "0.1"; break;
264 case 0x20020000: suf = "Z2/3"; break;
265 case 0x20020001: suf = "Z3"; break;
266 case 0x21000000: suf = "A"; break;
267 case 0x21010000: suf = "B"; m = 1; break;
268 case 0x21010001: suf = "B2"; m = 1; break;
270 case 0x24010000: suf = NULL;
271 puts ("PPC823EZTnnB2");
276 printf ("unknown MPC823 (0x%08x)", k);
280 printf ("PPC823ZTnn%s", suf);
282 printf (" at %s MHz:", strmhz (buf, clock));
284 printf (" %u kB I-Cache", checkicache () >> 10);
285 printf (" %u kB D-Cache", checkdcache () >> 10);
287 /* lets check and see if we're running on a 860T (or P?) */
289 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
290 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
291 puts (" FEC present");
303 #elif defined(CONFIG_MPC850)
305 static int check_CPU (long clock, uint pvr, uint immr)
307 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
311 /* the highest 16 bits should be 0x0050 for a 8xx */
313 if ((pvr >> 16) != 0x0050)
316 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
321 printf ("XPC850xxZT");
324 printf ("XPC850xxZTA");
327 printf ("XPC850xxZTB");
331 printf ("XPC850xxZTC");
335 printf ("unknown MPC850 (0x%08x)", k);
337 printf (" at %s MHz:", strmhz (buf, clock));
339 printf (" %u kB I-Cache", checkicache () >> 10);
340 printf (" %u kB D-Cache", checkdcache () >> 10);
342 /* lets check and see if we're running on a 850T (or P?) */
344 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
345 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
346 printf (" FEC present");
360 /* ------------------------------------------------------------------------- */
364 ulong clock = gd->cpu_clk;
365 uint immr = get_immr (0); /* Return full IMMR contents */
366 uint pvr = get_pvr ();
370 /* 850 has PARTNUM 20 */
371 /* 801 has PARTNUM 10 */
372 return check_CPU (clock, pvr, immr);
375 /* ------------------------------------------------------------------------- */
377 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
378 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
380 int checkicache (void)
382 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
383 volatile memctl8xx_t *memctl = &immap->im_memctl;
384 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
387 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
389 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
394 wr_ic_cst (IDC_UNALL);
395 wr_ic_cst (IDC_INVALL);
396 wr_ic_cst (IDC_DISABLE);
397 __asm__ volatile ("isync");
399 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
401 wr_ic_cst (IDC_LDLCK);
402 __asm__ volatile ("isync");
405 k += 0x10; /* the number of bytes in a cacheline */
408 wr_ic_cst (IDC_UNALL);
409 wr_ic_cst (IDC_INVALL);
412 wr_ic_cst (IDC_ENABLE);
414 wr_ic_cst (IDC_DISABLE);
416 __asm__ volatile ("isync");
421 /* ------------------------------------------------------------------------- */
423 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
424 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
425 /* call with cache disabled */
427 int checkdcache (void)
429 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
430 volatile memctl8xx_t *memctl = &immap->im_memctl;
431 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
434 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
436 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
441 wr_dc_cst (IDC_UNALL);
442 wr_dc_cst (IDC_INVALL);
443 wr_dc_cst (IDC_DISABLE);
445 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
447 wr_dc_cst (IDC_LDLCK);
449 k += 0x10; /* the number of bytes in a cacheline */
452 wr_dc_cst (IDC_UNALL);
453 wr_dc_cst (IDC_INVALL);
456 wr_dc_cst (IDC_ENABLE);
458 wr_dc_cst (IDC_DISABLE);
463 /* ------------------------------------------------------------------------- */
465 void upmconfig (uint upm, uint * table, uint size)
469 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
470 volatile memctl8xx_t *memctl = &immap->im_memctl;
472 for (i = 0; i < size; i++) {
473 memctl->memc_mdr = table[i]; /* (16-15) */
474 memctl->memc_mcr = addr | upm; /* (16-16) */
479 /* ------------------------------------------------------------------------- */
483 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
487 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
489 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
491 /* Interrupts and MMU off */
492 __asm__ volatile ("mtspr 81, 0");
493 __asm__ volatile ("mfmsr %0":"=r" (msr));
496 __asm__ volatile ("mtmsr %0"::"r" (msr));
499 * Trying to execute the next instruction at a non-existing address
500 * should cause a machine check, resulting in reset
502 #ifdef CONFIG_SYS_RESET_ADDRESS
503 addr = CONFIG_SYS_RESET_ADDRESS;
506 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
507 * - sizeof (ulong) is usually a valid address. Better pick an address
508 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
509 * "(ulong)-1" used to be a good choice for many systems...
511 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
513 ((void (*)(void)) addr) ();
517 #else /* CONFIG_LWMON */
520 * On the LWMON board, the MCLR reset input of the PIC's on the board
521 * uses a 47K/1n RC combination which has a 47us time constant. The
522 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
523 * and thus too short to reset the external hardware. So we use the
524 * watchdog to reset the board.
526 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
528 /* prevent triggering the watchdog */
529 disable_interrupts ();
531 /* make sure the watchdog is running */
532 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
534 /* wait for watchdog reset */
541 #endif /* CONFIG_LWMON */
543 /* ------------------------------------------------------------------------- */
546 * Get timebase clock frequency (like cpu_clk in Hz)
548 * See sections 14.2 and 14.6 of the User's Manual
550 unsigned long get_tbclk (void)
552 uint immr = get_immr (0); /* Return full IMMR contents */
553 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
554 ulong oscclk, factor, pll;
556 if (immap->im_clkrst.car_sccr & SCCR_TBS) {
557 return (gd->cpu_clk / 16);
560 pll = immap->im_clkrst.car_plprcr;
562 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
565 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
566 * factor is calculated as follows:
571 * factor = -----------------
574 * For older chips, it's just MF field of PLPRCR plus one.
576 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
577 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
578 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
580 factor = PLPRCR_val(MF)+1;
583 oscclk = gd->cpu_clk / factor;
585 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
588 return (oscclk / 16);
591 /* ------------------------------------------------------------------------- */
593 #if defined(CONFIG_WATCHDOG)
594 void watchdog_reset (void)
596 int re_enable = disable_interrupts ();
598 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
600 enable_interrupts ();
602 #endif /* CONFIG_WATCHDOG */
604 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
606 void reset_8xx_watchdog (volatile immap_t * immr)
608 # if defined(CONFIG_LWMON)
610 * The LWMON board uses a MAX6301 Watchdog
611 * with the trigger pin connected to port PA.7
613 * (The old board version used a MAX706TESA Watchdog, which
614 * had to be handled exactly the same.)
616 # define WATCHDOG_BIT 0x0100
617 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
618 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
619 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
621 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
622 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
624 * The KUP4 boards uses a TPS3705 Watchdog
625 * with the trigger pin connected to port PA.5
627 # define WATCHDOG_BIT 0x0400
628 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
629 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
630 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
632 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
635 * All other boards use the MPC8xx Internal Watchdog
637 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
638 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
639 # endif /* CONFIG_LWMON */
641 #endif /* CONFIG_WATCHDOG */
644 * Initializes on-chip ethernet controllers.
645 * to override, implement board_eth_init()
647 int cpu_eth_init(bd_t *bis)
649 #if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
652 #if defined(FEC_ENET)