2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
13 * written or collected and sometimes rewritten by
14 * Magnus Damm <damm@bitsmart.com>
16 * minor modifications by
17 * Wolfgang Denk <wd@denx.de>
25 #include <asm/cache.h>
26 #include <asm/cpm_8xx.h>
27 #include <linux/compiler.h>
30 #if defined(CONFIG_OF_LIBFDT)
31 #include <linux/libfdt.h>
32 #include <fdt_support.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 static int check_CPU(long clock, uint pvr, uint immr)
39 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
43 /* the highest 16 bits should be 0x0050 for a 860 */
45 if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
49 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
52 * Some boards use sockets so different CPUs can be used.
53 * We have to check chip version in run time.
56 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
57 case 0x08010004: /* Rev. A.0 */
58 printf("MPC866xxxZPnnA");
60 case 0x08000003: /* Rev. 0.3 */
61 printf("MPC866xxxZPnn");
63 case 0x09000000: /* 870/875/880/885 */
68 printf("unknown MPC86x (0x%08x)", k);
72 printf(" at %s MHz: ", strmhz(buf, clock));
74 print_size(checkicache(), " I-Cache ");
75 print_size(checkdcache(), " D-Cache");
77 /* do we have a FEC (860T/P or 852/859/866/885)? */
79 out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
80 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
81 printf(" FEC present");
88 /* ------------------------------------------------------------------------- */
92 ulong clock = gd->cpu_clk;
93 uint immr = get_immr(); /* Return full IMMR contents */
98 return check_CPU(clock, pvr, immr);
101 /* ------------------------------------------------------------------------- */
104 int checkicache(void)
106 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
107 memctl8xx_t __iomem *memctl = &immap->im_memctl;
108 u32 cacheon = rd_ic_cst() & IDC_ENABLED;
109 /* probe in flash memoryarea */
110 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
114 wr_ic_cst(IDC_UNALL);
115 wr_ic_cst(IDC_INVALL);
116 wr_ic_cst(IDC_DISABLE);
117 __asm__ volatile ("isync");
119 while (!((m = rd_ic_cst()) & IDC_CERR2)) {
121 wr_ic_cst(IDC_LDLCK);
122 __asm__ volatile ("isync");
125 k += 0x10; /* the number of bytes in a cacheline */
128 wr_ic_cst(IDC_UNALL);
129 wr_ic_cst(IDC_INVALL);
132 wr_ic_cst(IDC_ENABLE);
134 wr_ic_cst(IDC_DISABLE);
136 __asm__ volatile ("isync");
141 /* ------------------------------------------------------------------------- */
143 /* call with cache disabled */
145 int checkdcache(void)
147 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
148 memctl8xx_t __iomem *memctl = &immap->im_memctl;
149 u32 cacheon = rd_dc_cst() & IDC_ENABLED;
150 /* probe in flash memoryarea */
151 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
155 wr_dc_cst(IDC_UNALL);
156 wr_dc_cst(IDC_INVALL);
157 wr_dc_cst(IDC_DISABLE);
159 while (!((m = rd_dc_cst()) & IDC_CERR2)) {
161 wr_dc_cst(IDC_LDLCK);
163 k += 0x10; /* the number of bytes in a cacheline */
166 wr_dc_cst(IDC_UNALL);
167 wr_dc_cst(IDC_INVALL);
170 wr_dc_cst(IDC_ENABLE);
172 wr_dc_cst(IDC_DISABLE);
177 /* ------------------------------------------------------------------------- */
179 void upmconfig(uint upm, uint *table, uint size)
183 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
184 memctl8xx_t __iomem *memctl = &immap->im_memctl;
186 for (i = 0; i < size; i++) {
187 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
188 out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
193 /* ------------------------------------------------------------------------- */
195 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
199 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
201 /* Checkstop Reset enable */
202 setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
204 /* Interrupts and MMU off */
205 __asm__ volatile ("mtspr 81, 0");
206 __asm__ volatile ("mfmsr %0" : "=r" (msr));
209 __asm__ volatile ("mtmsr %0" : : "r" (msr));
212 * Trying to execute the next instruction at a non-existing address
213 * should cause a machine check, resulting in reset
215 #ifdef CONFIG_SYS_RESET_ADDRESS
216 addr = CONFIG_SYS_RESET_ADDRESS;
219 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
220 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
221 * Better pick an address known to be invalid on your system and assign
222 * it to CONFIG_SYS_RESET_ADDRESS.
223 * "(ulong)-1" used to be a good choice for many systems...
225 addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
227 ((void (*)(void)) addr)();
231 /* ------------------------------------------------------------------------- */
234 * Get timebase clock frequency (like cpu_clk in Hz)
236 * See sections 14.2 and 14.6 of the User's Manual
238 unsigned long get_tbclk(void)
240 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
241 ulong oscclk, factor, pll;
243 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
244 return gd->cpu_clk / 16;
246 pll = in_be32(&immap->im_clkrst.car_plprcr);
248 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
251 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
252 * factor is calculated as follows:
257 * factor = -----------------
261 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
262 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
264 oscclk = gd->cpu_clk / factor;
266 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
273 /* ------------------------------------------------------------------------- */
275 #if defined(CONFIG_WATCHDOG)
276 void watchdog_reset(void)
278 int re_enable = disable_interrupts();
280 reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
284 #endif /* CONFIG_WATCHDOG */
286 #if defined(CONFIG_WATCHDOG)
288 void reset_8xx_watchdog(immap_t __iomem *immr)
291 * All other boards use the MPC8xx Internal Watchdog
293 out_be16(&immr->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
294 out_be16(&immr->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
296 #endif /* CONFIG_WATCHDOG */
299 * Initializes on-chip ethernet controllers.
300 * to override, implement board_eth_init()
302 int cpu_eth_init(bd_t *bis)
304 #if defined(CONFIG_MPC8XX_FEC)