2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
42 #include <asm/cache.h>
43 #include <linux/compiler.h>
45 #if defined(CONFIG_OF_LIBFDT)
47 #include <libfdt_env.h>
48 #include <fdt_support.h>
51 DECLARE_GLOBAL_DATA_PTR;
53 static char *cpu_warning = "\n " \
54 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
56 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
57 !defined(CONFIG_MPC862))
59 static int check_CPU (long clock, uint pvr, uint immr)
62 # if defined(CONFIG_MPC855)
64 # elif defined(CONFIG_MPC860P)
69 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
76 /* the highest 16 bits should be 0x0050 for a 860 */
78 if ((pvr >> 16) != 0x0050)
81 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
86 * Some boards use sockets so different CPUs can be used.
87 * We have to check chip version in run time.
90 case 0x00020001: pre = 'P'; break;
91 case 0x00030001: break;
92 case 0x00120003: suf = "A"; break;
93 case 0x00130003: suf = "A3"; break;
95 case 0x00200004: suf = "B"; break;
97 case 0x00300004: suf = "C"; break;
98 case 0x00310004: suf = "C1"; m = 1; break;
100 case 0x00200064: mid = "SR"; suf = "B"; break;
101 case 0x00300065: mid = "SR"; suf = "C"; break;
102 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
103 case 0x05010000: suf = "D3"; m = 1; break;
104 case 0x05020000: suf = "D4"; m = 1; break;
105 /* this value is not documented anywhere */
106 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
107 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
108 case 0x08010004: /* Rev. A.0 */
111 case 0x08000003: /* Rev. 0.3 */
115 # if defined(CONFIG_MPC852T)
117 # elif defined(CONFIG_MPC859T)
119 # elif defined(CONFIG_MPC859DSL)
121 # elif defined(CONFIG_MPC866T)
124 "PC866x"; /* Unknown chip from MPC866 family */
127 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
129 id_str = "PC885"; /* 870/875/880/885 */
132 default: suf = NULL; break;
136 id_str = "PC86x"; /* Unknown 86x chip */
138 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
140 printf ("unknown M%s (0x%08x)", id_str, k);
143 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
144 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
146 CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
147 ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
148 CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
149 ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
152 printf (" at %s MHz: ", strmhz (buf, clock));
154 printf ("%u kB I-Cache %u kB D-Cache",
155 checkicache () >> 10,
159 /* do we have a FEC (860T/P or 852/859/866/885)? */
161 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
162 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
163 printf (" FEC present");
173 if(clock != measure_gclk()) {
174 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
181 #elif defined(CONFIG_MPC862)
183 static int check_CPU (long clock, uint pvr, uint immr)
185 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
189 __maybe_unused char *mid = "xx";
192 /* the highest 16 bits should be 0x0050 for a 8xx */
194 if ((pvr >> 16) != 0x0050)
197 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
202 /* this value is not documented anywhere */
203 case 0x06000000: mid = "P"; suf = "0"; break;
204 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
205 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
206 default: suf = NULL; break;
209 #ifndef CONFIG_MPC857
211 printf ("%cPC862%sZPnn%s", pre, mid, suf);
213 printf ("unknown MPC862 (0x%08x)", k);
216 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
218 printf ("unknown MPC857 (0x%08x)", k);
221 printf (" at %s MHz:", strmhz (buf, clock));
223 printf (" %u kB I-Cache", checkicache () >> 10);
224 printf (" %u kB D-Cache", checkdcache () >> 10);
226 /* lets check and see if we're running on a 862T (or P?) */
228 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
229 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
230 printf (" FEC present");
242 #elif defined(CONFIG_MPC823)
244 static int check_CPU (long clock, uint pvr, uint immr)
246 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
251 /* the highest 16 bits should be 0x0050 for a 8xx */
253 if ((pvr >> 16) != 0x0050)
256 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
261 case 0x20000000: suf = "0"; break;
262 case 0x20010000: suf = "0.1"; break;
263 case 0x20020000: suf = "Z2/3"; break;
264 case 0x20020001: suf = "Z3"; break;
265 case 0x21000000: suf = "A"; break;
266 case 0x21010000: suf = "B"; m = 1; break;
267 case 0x21010001: suf = "B2"; m = 1; break;
269 case 0x24010000: suf = NULL;
270 puts ("PPC823EZTnnB2");
275 printf ("unknown MPC823 (0x%08x)", k);
279 printf ("PPC823ZTnn%s", suf);
281 printf (" at %s MHz:", strmhz (buf, clock));
283 printf (" %u kB I-Cache", checkicache () >> 10);
284 printf (" %u kB D-Cache", checkdcache () >> 10);
286 /* lets check and see if we're running on a 860T (or P?) */
288 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
289 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
290 puts (" FEC present");
302 #elif defined(CONFIG_MPC850)
304 static int check_CPU (long clock, uint pvr, uint immr)
306 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
310 /* the highest 16 bits should be 0x0050 for a 8xx */
312 if ((pvr >> 16) != 0x0050)
315 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
320 printf ("XPC850xxZT");
323 printf ("XPC850xxZTA");
326 printf ("XPC850xxZTB");
330 printf ("XPC850xxZTC");
334 printf ("unknown MPC850 (0x%08x)", k);
336 printf (" at %s MHz:", strmhz (buf, clock));
338 printf (" %u kB I-Cache", checkicache () >> 10);
339 printf (" %u kB D-Cache", checkdcache () >> 10);
341 /* lets check and see if we're running on a 850T (or P?) */
343 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
344 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
345 printf (" FEC present");
359 /* ------------------------------------------------------------------------- */
363 ulong clock = gd->cpu_clk;
364 uint immr = get_immr (0); /* Return full IMMR contents */
365 uint pvr = get_pvr ();
369 /* 850 has PARTNUM 20 */
370 /* 801 has PARTNUM 10 */
371 return check_CPU (clock, pvr, immr);
374 /* ------------------------------------------------------------------------- */
376 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
377 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
379 int checkicache (void)
381 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
382 volatile memctl8xx_t *memctl = &immap->im_memctl;
383 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
386 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
388 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
393 wr_ic_cst (IDC_UNALL);
394 wr_ic_cst (IDC_INVALL);
395 wr_ic_cst (IDC_DISABLE);
396 __asm__ volatile ("isync");
398 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
400 wr_ic_cst (IDC_LDLCK);
401 __asm__ volatile ("isync");
404 k += 0x10; /* the number of bytes in a cacheline */
407 wr_ic_cst (IDC_UNALL);
408 wr_ic_cst (IDC_INVALL);
411 wr_ic_cst (IDC_ENABLE);
413 wr_ic_cst (IDC_DISABLE);
415 __asm__ volatile ("isync");
420 /* ------------------------------------------------------------------------- */
422 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
423 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
424 /* call with cache disabled */
426 int checkdcache (void)
428 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
429 volatile memctl8xx_t *memctl = &immap->im_memctl;
430 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
433 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
435 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
440 wr_dc_cst (IDC_UNALL);
441 wr_dc_cst (IDC_INVALL);
442 wr_dc_cst (IDC_DISABLE);
444 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
446 wr_dc_cst (IDC_LDLCK);
448 k += 0x10; /* the number of bytes in a cacheline */
451 wr_dc_cst (IDC_UNALL);
452 wr_dc_cst (IDC_INVALL);
455 wr_dc_cst (IDC_ENABLE);
457 wr_dc_cst (IDC_DISABLE);
462 /* ------------------------------------------------------------------------- */
464 void upmconfig (uint upm, uint * table, uint size)
468 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
469 volatile memctl8xx_t *memctl = &immap->im_memctl;
471 for (i = 0; i < size; i++) {
472 memctl->memc_mdr = table[i]; /* (16-15) */
473 memctl->memc_mcr = addr | upm; /* (16-16) */
478 /* ------------------------------------------------------------------------- */
482 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
486 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
488 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
490 /* Interrupts and MMU off */
491 __asm__ volatile ("mtspr 81, 0");
492 __asm__ volatile ("mfmsr %0":"=r" (msr));
495 __asm__ volatile ("mtmsr %0"::"r" (msr));
498 * Trying to execute the next instruction at a non-existing address
499 * should cause a machine check, resulting in reset
501 #ifdef CONFIG_SYS_RESET_ADDRESS
502 addr = CONFIG_SYS_RESET_ADDRESS;
505 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
506 * - sizeof (ulong) is usually a valid address. Better pick an address
507 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
508 * "(ulong)-1" used to be a good choice for many systems...
510 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
512 ((void (*)(void)) addr) ();
516 #else /* CONFIG_LWMON */
519 * On the LWMON board, the MCLR reset input of the PIC's on the board
520 * uses a 47K/1n RC combination which has a 47us time constant. The
521 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
522 * and thus too short to reset the external hardware. So we use the
523 * watchdog to reset the board.
525 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
527 /* prevent triggering the watchdog */
528 disable_interrupts ();
530 /* make sure the watchdog is running */
531 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
533 /* wait for watchdog reset */
540 #endif /* CONFIG_LWMON */
542 /* ------------------------------------------------------------------------- */
545 * Get timebase clock frequency (like cpu_clk in Hz)
547 * See sections 14.2 and 14.6 of the User's Manual
549 unsigned long get_tbclk (void)
551 uint immr = get_immr (0); /* Return full IMMR contents */
552 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
553 ulong oscclk, factor, pll;
555 if (immap->im_clkrst.car_sccr & SCCR_TBS) {
556 return (gd->cpu_clk / 16);
559 pll = immap->im_clkrst.car_plprcr;
561 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
564 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
565 * factor is calculated as follows:
570 * factor = -----------------
573 * For older chips, it's just MF field of PLPRCR plus one.
575 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
576 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
577 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
579 factor = PLPRCR_val(MF)+1;
582 oscclk = gd->cpu_clk / factor;
584 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
587 return (oscclk / 16);
590 /* ------------------------------------------------------------------------- */
592 #if defined(CONFIG_WATCHDOG)
593 void watchdog_reset (void)
595 int re_enable = disable_interrupts ();
597 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
599 enable_interrupts ();
601 #endif /* CONFIG_WATCHDOG */
603 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
605 void reset_8xx_watchdog (volatile immap_t * immr)
607 # if defined(CONFIG_LWMON)
609 * The LWMON board uses a MAX6301 Watchdog
610 * with the trigger pin connected to port PA.7
612 * (The old board version used a MAX706TESA Watchdog, which
613 * had to be handled exactly the same.)
615 # define WATCHDOG_BIT 0x0100
616 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
617 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
618 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
620 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
621 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
623 * The KUP4 boards uses a TPS3705 Watchdog
624 * with the trigger pin connected to port PA.5
626 # define WATCHDOG_BIT 0x0400
627 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
628 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
629 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
631 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
634 * All other boards use the MPC8xx Internal Watchdog
636 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
637 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
638 # endif /* CONFIG_LWMON */
640 #endif /* CONFIG_WATCHDOG */
643 * Initializes on-chip ethernet controllers.
644 * to override, implement board_eth_init()
646 int cpu_eth_init(bd_t *bis)
648 #if defined(SCC_ENET) && defined(CONFIG_CMD_NET)
651 #if defined(FEC_ENET)