2 * Copyright 2004, 2007, 2011 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
33 #include <asm-offsets.h>
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
43 #include <asm/u-boot.h>
46 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
50 * Set up GOT: Global Offset Table
52 * Use r12 to access the GOT
55 GOT_ENTRY(_GOT2_TABLE_)
56 GOT_ENTRY(_FIXUP_TABLE_)
59 GOT_ENTRY(_start_of_vectors)
60 GOT_ENTRY(_end_of_vectors)
61 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * r3 - 1st arg to board_init(): IMMP pointer
70 * r4 - 2nd arg to board_init(): boot flag
73 .long 0x27051956 /* U-Boot Magic Number */
76 .ascii U_BOOT_VERSION_STRING, "\0"
83 /* the boot code is located below the exception table */
85 .globl _start_of_vectors
89 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
91 /* Data Storage exception. */
92 STD_EXCEPTION(0x300, DataStorage, UnknownException)
94 /* Instruction Storage exception. */
95 STD_EXCEPTION(0x400, InstStorage, UnknownException)
97 /* External Interrupt exception. */
98 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
100 /* Alignment exception. */
103 EXCEPTION_PROLOG(SRR0, SRR1)
108 addi r3,r1,STACK_FRAME_OVERHEAD
109 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
111 /* Program check exception */
114 EXCEPTION_PROLOG(SRR0, SRR1)
115 addi r3,r1,STACK_FRAME_OVERHEAD
116 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
119 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
121 /* I guess we could implement decrementer, and may have
122 * to someday for timekeeping.
124 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
125 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
126 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
127 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
128 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
129 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
130 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
131 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
132 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
133 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
134 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
135 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
136 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
137 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
138 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
139 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
140 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
141 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
142 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
143 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
144 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
145 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
146 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
148 .globl _end_of_vectors
155 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
156 * address specified by the BPTR
159 #ifdef CONFIG_SYS_RAMBOOT
160 /* disable everything */
167 /* Invalidate BATs */
170 /* Invalidate all of TLB before MMU turn on */
175 /* init the L2 cache */
177 ori r3, r3, L2_INIT@l
179 /* invalidate the L2 cache */
180 bl l2cache_invalidate
185 * Calculate absolute address in FLASH and jump there
186 *------------------------------------------------------*/
187 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
188 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
189 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
194 /* let the C-code set up the rest */
196 /* Be careful to keep code relocatable ! */
197 /*------------------------------------------------------*/
198 /* perform low-level init */
200 /* enable extended addressing */
207 * Cache must be enabled here for stack-in-cache trick.
208 * This means we need to enable the BATS.
209 * Cache should be turned on after BATs, since by default
210 * everything is write-through.
213 /* enable address translation */
215 ori r5, r5, (MSR_IR | MSR_DR)
216 lis r3,addr_trans_enabled@h
217 ori r3, r3, addr_trans_enabled@l
223 /* enable and invalidate the data cache */
224 /* bl l1dcache_enable */
232 #ifdef CONFIG_SYS_INIT_RAM_LOCK
237 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
241 /* set up the stack pointer in our newly created
243 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
244 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
246 li r0, 0 /* Make room for stack frame header and */
247 stwu r0, -4(r1) /* clear final stack frame so that */
248 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
250 GET_GOT /* initialize GOT access */
252 /* run low-level CPU init code (from Flash) */
258 /* Load PX_AUX register address in r4 */
261 /* Load contents of PX_AUX in r3 bits 24 to 31*/
264 /* Mask and obtain the bit in r3 */
265 rlwinm. r3, r3, 0, 24, 24
266 /* If not zero, jump and continue with u-boot */
269 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
271 /* Set the MSB of the register value */
273 /* Write value in r3 back to PX_AUX */
276 /* Get the address to jump to in r3*/
277 lis r3, CONFIG_SYS_DIAG_ADDR@h
278 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
280 /* Load the LR with the branch address */
283 /* Branch to diagnostic */
289 /* bl l2cache_enable */
291 /* run 1st part of board init code (from Flash) */
295 /* NOTREACHED - board_init_f() does not return */
297 .globl invalidate_bats
301 /* invalidate BATs */
325 #define CONFIG_BAT_PAIR(n) \
326 lis r4, CONFIG_SYS_IBAT##n##L@h; \
327 ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
328 lis r3, CONFIG_SYS_IBAT##n##U@h; \
329 ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \
330 mtspr IBAT##n##L, r4; \
331 mtspr IBAT##n##U, r3; \
332 lis r4, CONFIG_SYS_DBAT##n##L@h; \
333 ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \
334 lis r3, CONFIG_SYS_DBAT##n##U@h; \
335 ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \
336 mtspr DBAT##n##L, r4; \
337 mtspr DBAT##n##U, r3;
342 * Set up the final BAT registers now that setup is done.
345 * 1) Address translation is enabled upon entry
346 * 2) The boot rom is still accessible via 1:1 translation
354 * When we disable address translation, we will get 1:1 (VA==PA)
355 * translation. The only place we know for sure is safe for that is
356 * the bootrom where we originally started out. Pop back into there.
358 lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
359 ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
360 addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
362 /* disable address translation */
364 rlwinm r3, r3, 0, 28, 25
370 #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
371 && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
385 /* Turn translation back on and return */
387 ori r3, r3, (MSR_IR | MSR_DR)
395 * Set up bats needed early on - this is usually the BAT for the
396 * stack-in-cache, the Flash, and CCSR space
401 lis r4, CONFIG_SYS_IBAT3L@h
402 ori r4, r4, CONFIG_SYS_IBAT3L@l
403 lis r3, CONFIG_SYS_IBAT3U@h
404 ori r3, r3, CONFIG_SYS_IBAT3U@l
410 lis r4, CONFIG_SYS_DBAT3L@h
411 ori r4, r4, CONFIG_SYS_DBAT3L@l
412 lis r3, CONFIG_SYS_DBAT3U@h
413 ori r3, r3, CONFIG_SYS_DBAT3U@l
419 lis r4, CONFIG_SYS_IBAT5L@h
420 ori r4, r4, CONFIG_SYS_IBAT5L@l
421 lis r3, CONFIG_SYS_IBAT5U@h
422 ori r3, r3, CONFIG_SYS_IBAT5U@l
428 lis r4, CONFIG_SYS_DBAT5L@h
429 ori r4, r4, CONFIG_SYS_DBAT5L@l
430 lis r3, CONFIG_SYS_DBAT5U@h
431 ori r3, r3, CONFIG_SYS_DBAT5U@l
437 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
438 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
439 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
440 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
446 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
447 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
448 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
449 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
454 #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
456 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
457 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
458 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
459 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
465 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
466 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
467 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
468 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
488 .globl disable_addr_trans
490 /* disable address translation */
493 andi. r0, r3, (MSR_IR | MSR_DR)
501 * This code finishes saving the registers to the exception frame
502 * and jumps to the appropriate handler for the exception.
503 * Register r21 is pointer into trap frame, r1 has new stack pointer.
505 .globl transfer_to_handler
516 andi. r24,r23,0x3f00 /* get vector offset */
520 mtspr SPRG2,r22 /* r1 is now kernel sp */
521 lwz r24,0(r23) /* virtual address of handler */
522 lwz r23,4(r23) /* where to go when done */
527 rfi /* jump to handler, enable MMU */
530 mfmsr r28 /* Disable interrupts */
534 SYNC /* Some chip revs need this... */
549 lwz r2,_NIP(r1) /* Restore environment */
576 * Description: Input 8 bits
585 * Description: Output 8 bits
594 * Description: Output 16 bits
603 * Description: Byte reverse and output 16 bits
612 * Description: Output 32 bits
621 * Description: Byte reverse and output 32 bits
630 * Description: Input 16 bits
639 * Description: Input 16 bits and byte reverse
648 * Description: Input 32 bits
657 * Description: Input 32 bits and byte reverse
665 * void relocate_code (addr_sp, gd, addr_moni)
667 * This "function" does not return, instead it continues in RAM
668 * after relocating the monitor code.
672 * r5 = length in bytes
678 mr r1, r3 /* Set new stack pointer */
679 mr r9, r4 /* Save copy of Global Data pointer */
680 mr r10, r5 /* Save copy of Destination Address */
683 mr r3, r5 /* Destination Address */
684 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
685 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
686 lwz r5, GOT(__init_end)
688 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
693 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
699 /* First our own GOT */
701 /* then the one used by the C code */
710 beq cr1,4f /* In place copy is not necessary */
711 beq 7f /* Protect against 0 count */
729 * Now flush the cache: note that we must start from a cache aligned
730 * address. Otherwise we might miss one cache line.
734 beq 7f /* Always flush prefetch queue in any case */
742 sync /* Wait for all dcbst to complete on bus */
748 7: sync /* Wait for all icbi to complete on bus */
752 * We are done. Do not return, instead branch to second part of board
753 * initialization, now running from RAM.
755 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
761 * Relocation Function, r12 point to got2+0x8000
763 * Adjust got2 pointers, no need to check for 0, this code
764 * already puts a few entries in the table.
766 li r0,__got2_entries@sectoff@l
767 la r3,GOT(_GOT2_TABLE_)
768 lwz r11,GOT(_GOT2_TABLE_)
780 * Now adjust the fixups and the pointers to the fixups
781 * in case we need to move ourselves again.
783 li r0,__fixup_entries@sectoff@l
784 lwz r3,GOT(_FIXUP_TABLE_)
800 * Now clear BSS segment
802 lwz r3,GOT(__bss_start)
803 lwz r4,GOT(__bss_end__)
815 mr r3, r9 /* Init Date pointer */
816 mr r4, r10 /* Destination Address */
819 /* not reached - end relocate_code */
820 /*-----------------------------------------------------------------------*/
823 * Copy exception vector code to low memory
826 * r7: source address, r8: end address, r9: target address
830 mflr r4 /* save link register */
833 lwz r8, GOT(_end_of_vectors)
835 li r9, 0x100 /* reset vector always at 0x100 */
838 bgelr /* return if r7>=r8 - just in case */
848 * relocate `hdlr' and `int_return' entries
850 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
851 li r8, Alignment - _start + EXC_OFF_SYS_RESET
854 addi r7, r7, 0x100 /* next exception vector */
858 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
861 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
864 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
865 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
868 addi r7, r7, 0x100 /* next exception vector */
872 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
873 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
876 addi r7, r7, 0x100 /* next exception vector */
880 /* enable execptions from RAM vectors */
884 ori r7,r7,MSR_ME /* Enable Machine Check */
887 mtlr r4 /* restore link register */
890 .globl enable_ext_addr
893 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
894 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
900 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
903 /* Special sequence needed to update CCSRBAR itself */
904 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
905 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
907 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
908 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
910 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
912 stw r5, 0(r4) /* Store physical value of CCSR */
915 lis r5, CONFIG_SYS_TEXT_BASE@h
916 ori r5,r5,CONFIG_SYS_TEXT_BASE@l
920 /* Use VA of CCSR to do read */
921 lis r3, CONFIG_SYS_CCSRBAR@h
922 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
928 #ifdef CONFIG_SYS_INIT_RAM_LOCK
930 /* Allocate Initial RAM in data cache.
932 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
933 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
934 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
935 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
942 /* Lock the data cache */
951 /* Lock the first way of the data cache */
954 #if defined(CONFIG_ALTIVEC)
964 .globl unlock_ram_in_cache
966 /* invalidate the INIT_RAM section */
967 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
968 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
969 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
970 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
975 sync /* Wait for all icbi to complete on bus */
978 /* Unlock the data cache and invalidate it */
990 /* Unlock the first way of the data cache */
994 #ifdef CONFIG_ALTIVEC