2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
35 #include <timestamp.h>
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
53 * Set up GOT: Global Offset Table
55 * Use r12 to access the GOT
58 GOT_ENTRY(_GOT2_TABLE_)
59 GOT_ENTRY(_FIXUP_TABLE_)
62 GOT_ENTRY(_start_of_vectors)
63 GOT_ENTRY(_end_of_vectors)
64 GOT_ENTRY(transfer_to_handler)
68 GOT_ENTRY(__bss_start)
72 * r3 - 1st arg to board_init(): IMMP pointer
73 * r4 - 2nd arg to board_init(): boot flag
76 .long 0x27051956 /* U-Boot Magic Number */
80 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
81 .ascii CONFIG_IDENT_STRING, "\0"
86 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
90 . = EXC_OFF_SYS_RESET + 0x10
94 li r21, BOOTFLAG_WARM /* Software reboot */
98 /* the boot code is located below the exception table */
100 .globl _start_of_vectors
104 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
106 /* Data Storage exception. */
107 STD_EXCEPTION(0x300, DataStorage, UnknownException)
109 /* Instruction Storage exception. */
110 STD_EXCEPTION(0x400, InstStorage, UnknownException)
112 /* External Interrupt exception. */
113 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
115 /* Alignment exception. */
118 EXCEPTION_PROLOG(SRR0, SRR1)
123 addi r3,r1,STACK_FRAME_OVERHEAD
124 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
126 /* Program check exception */
129 EXCEPTION_PROLOG(SRR0, SRR1)
130 addi r3,r1,STACK_FRAME_OVERHEAD
131 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
134 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
136 /* I guess we could implement decrementer, and may have
137 * to someday for timekeeping.
139 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
140 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
141 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
142 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
143 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
144 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
145 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
146 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
147 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
148 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
149 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
150 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
151 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
152 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
153 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
154 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
155 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
156 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
157 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
158 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
159 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
160 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
161 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
163 .globl _end_of_vectors
171 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
172 * address specified by the BPTR
175 #ifdef CONFIG_SYS_RAMBOOT
176 /* disable everything */
183 /* Invalidate BATs */
186 /* Invalidate all of TLB before MMU turn on */
191 /* init the L2 cache */
193 ori r3, r3, L2_INIT@l
195 /* invalidate the L2 cache */
196 bl l2cache_invalidate
201 * Calculate absolute address in FLASH and jump there
202 *------------------------------------------------------*/
203 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
204 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
205 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
210 /* let the C-code set up the rest */
212 /* Be careful to keep code relocatable ! */
213 /*------------------------------------------------------*/
214 /* perform low-level init */
216 /* enable extended addressing */
223 * Cache must be enabled here for stack-in-cache trick.
224 * This means we need to enable the BATS.
225 * Cache should be turned on after BATs, since by default
226 * everything is write-through.
229 /* enable address translation */
231 ori r5, r5, (MSR_IR | MSR_DR)
232 lis r3,addr_trans_enabled@h
233 ori r3, r3, addr_trans_enabled@l
239 /* enable and invalidate the data cache */
240 /* bl l1dcache_enable */
248 #ifdef CONFIG_SYS_INIT_RAM_LOCK
253 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
257 /* set up the stack pointer in our newly created
259 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
260 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
262 li r0, 0 /* Make room for stack frame header and */
263 stwu r0, -4(r1) /* clear final stack frame so that */
264 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
266 GET_GOT /* initialize GOT access */
268 /* run low-level CPU init code (from Flash) */
274 /* Load PX_AUX register address in r4 */
277 /* Load contents of PX_AUX in r3 bits 24 to 31*/
280 /* Mask and obtain the bit in r3 */
281 rlwinm. r3, r3, 0, 24, 24
282 /* If not zero, jump and continue with u-boot */
285 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
287 /* Set the MSB of the register value */
289 /* Write value in r3 back to PX_AUX */
292 /* Get the address to jump to in r3*/
293 lis r3, CONFIG_SYS_DIAG_ADDR@h
294 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
296 /* Load the LR with the branch address */
299 /* Branch to diagnostic */
305 /* bl l2cache_enable */
309 /* run 1st part of board init code (from Flash) */
315 .globl invalidate_bats
319 /* invalidate BATs */
346 * Set up bats needed early on - this is usually the BAT for the
347 * stack-in-cache, the Flash, and CCSR space
352 lis r4, CONFIG_SYS_IBAT3L@h
353 ori r4, r4, CONFIG_SYS_IBAT3L@l
354 lis r3, CONFIG_SYS_IBAT3U@h
355 ori r3, r3, CONFIG_SYS_IBAT3U@l
361 lis r4, CONFIG_SYS_DBAT3L@h
362 ori r4, r4, CONFIG_SYS_DBAT3L@l
363 lis r3, CONFIG_SYS_DBAT3U@h
364 ori r3, r3, CONFIG_SYS_DBAT3U@l
370 lis r4, CONFIG_SYS_IBAT5L@h
371 ori r4, r4, CONFIG_SYS_IBAT5L@l
372 lis r3, CONFIG_SYS_IBAT5U@h
373 ori r3, r3, CONFIG_SYS_IBAT5U@l
379 lis r4, CONFIG_SYS_DBAT5L@h
380 ori r4, r4, CONFIG_SYS_DBAT5L@l
381 lis r3, CONFIG_SYS_DBAT5U@h
382 ori r3, r3, CONFIG_SYS_DBAT5U@l
388 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
389 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
390 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
391 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
397 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
398 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
399 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
400 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
405 #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
407 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
408 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
409 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
410 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
416 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
417 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
418 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
419 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
439 .globl disable_addr_trans
441 /* disable address translation */
444 andi. r0, r3, (MSR_IR | MSR_DR)
452 * This code finishes saving the registers to the exception frame
453 * and jumps to the appropriate handler for the exception.
454 * Register r21 is pointer into trap frame, r1 has new stack pointer.
456 .globl transfer_to_handler
467 andi. r24,r23,0x3f00 /* get vector offset */
471 mtspr SPRG2,r22 /* r1 is now kernel sp */
472 lwz r24,0(r23) /* virtual address of handler */
473 lwz r23,4(r23) /* where to go when done */
478 rfi /* jump to handler, enable MMU */
481 mfmsr r28 /* Disable interrupts */
485 SYNC /* Some chip revs need this... */
500 lwz r2,_NIP(r1) /* Restore environment */
527 * Description: Input 8 bits
536 * Description: Output 8 bits
545 * Description: Output 16 bits
554 * Description: Byte reverse and output 16 bits
563 * Description: Output 32 bits
572 * Description: Byte reverse and output 32 bits
581 * Description: Input 16 bits
590 * Description: Input 16 bits and byte reverse
599 * Description: Input 32 bits
608 * Description: Input 32 bits and byte reverse
616 * void relocate_code (addr_sp, gd, addr_moni)
618 * This "function" does not return, instead it continues in RAM
619 * after relocating the monitor code.
623 * r5 = length in bytes
629 mr r1, r3 /* Set new stack pointer */
630 mr r9, r4 /* Save copy of Global Data pointer */
631 mr r10, r5 /* Save copy of Destination Address */
634 mr r3, r5 /* Destination Address */
635 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
636 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
637 lwz r5, GOT(__init_end)
639 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
644 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
650 /* First our own GOT */
652 /* then the one used by the C code */
661 beq cr1,4f /* In place copy is not necessary */
662 beq 7f /* Protect against 0 count */
680 * Now flush the cache: note that we must start from a cache aligned
681 * address. Otherwise we might miss one cache line.
685 beq 7f /* Always flush prefetch queue in any case */
693 sync /* Wait for all dcbst to complete on bus */
699 7: sync /* Wait for all icbi to complete on bus */
703 * We are done. Do not return, instead branch to second part of board
704 * initialization, now running from RAM.
706 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
712 * Relocation Function, r12 point to got2+0x8000
714 * Adjust got2 pointers, no need to check for 0, this code
715 * already puts a few entries in the table.
717 li r0,__got2_entries@sectoff@l
718 la r3,GOT(_GOT2_TABLE_)
719 lwz r11,GOT(_GOT2_TABLE_)
731 * Now adjust the fixups and the pointers to the fixups
732 * in case we need to move ourselves again.
734 li r0,__fixup_entries@sectoff@l
735 lwz r3,GOT(_FIXUP_TABLE_)
749 * Now clear BSS segment
751 lwz r3,GOT(__bss_start)
764 mr r3, r9 /* Init Date pointer */
765 mr r4, r10 /* Destination Address */
768 /* not reached - end relocate_code */
769 /*-----------------------------------------------------------------------*/
772 * Copy exception vector code to low memory
775 * r7: source address, r8: end address, r9: target address
779 mflr r4 /* save link register */
782 lwz r8, GOT(_end_of_vectors)
784 li r9, 0x100 /* reset vector always at 0x100 */
787 bgelr /* return if r7>=r8 - just in case */
797 * relocate `hdlr' and `int_return' entries
799 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
800 li r8, Alignment - _start + EXC_OFF_SYS_RESET
803 addi r7, r7, 0x100 /* next exception vector */
807 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
810 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
813 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
814 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
817 addi r7, r7, 0x100 /* next exception vector */
821 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
822 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
825 addi r7, r7, 0x100 /* next exception vector */
829 /* enable execptions from RAM vectors */
833 ori r7,r7,MSR_ME /* Enable Machine Check */
836 mtlr r4 /* restore link register */
839 .globl enable_ext_addr
842 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
843 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
849 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
852 /* Special sequence needed to update CCSRBAR itself */
853 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
854 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
856 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
857 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
859 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
861 stw r5, 0(r4) /* Store physical value of CCSR */
865 ori r5,r5,TEXT_BASE@l
869 /* Use VA of CCSR to do read */
870 lis r3, CONFIG_SYS_CCSRBAR@h
871 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
877 #ifdef CONFIG_SYS_INIT_RAM_LOCK
879 /* Allocate Initial RAM in data cache.
881 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
882 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
883 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
884 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
891 /* Lock the data cache */
900 /* Lock the first way of the data cache */
903 #if defined(CONFIG_ALTIVEC)
913 .globl unlock_ram_in_cache
915 /* invalidate the INIT_RAM section */
916 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
917 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
918 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
919 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
924 sync /* Wait for all icbi to complete on bus */
927 /* Unlock the data cache and invalidate it */
939 /* Unlock the first way of the data cache */
943 #ifdef CONFIG_ALTIVEC