2 * Copyright 2004, 2007, 2011 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
11 * The processor starts at 0xfff00100 and the code is executed
12 * from flash. The code is organized to be at an other address
13 * in memory, but as long we don't jump around before relocating.
14 * board_init lies at a quite high address and when the cpu has
15 * jumped there, everything is ok.
17 #include <asm-offsets.h>
22 #include <ppc_asm.tmpl>
25 #include <asm/cache.h>
27 #include <asm/u-boot.h>
30 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
34 * Set up GOT: Global Offset Table
36 * Use r12 to access the GOT
39 GOT_ENTRY(_GOT2_TABLE_)
40 GOT_ENTRY(_FIXUP_TABLE_)
43 GOT_ENTRY(_start_of_vectors)
44 GOT_ENTRY(_end_of_vectors)
45 GOT_ENTRY(transfer_to_handler)
49 GOT_ENTRY(__bss_start)
53 * r3 - 1st arg to board_init(): IMMP pointer
54 * r4 - 2nd arg to board_init(): boot flag
57 .long 0x27051956 /* U-Boot Magic Number */
60 .ascii U_BOOT_VERSION_STRING, "\0"
67 /* the boot code is located below the exception table */
69 .globl _start_of_vectors
73 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
75 /* Data Storage exception. */
76 STD_EXCEPTION(0x300, DataStorage, UnknownException)
78 /* Instruction Storage exception. */
79 STD_EXCEPTION(0x400, InstStorage, UnknownException)
81 /* External Interrupt exception. */
82 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
84 /* Alignment exception. */
87 EXCEPTION_PROLOG(SRR0, SRR1)
92 addi r3,r1,STACK_FRAME_OVERHEAD
93 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
95 /* Program check exception */
98 EXCEPTION_PROLOG(SRR0, SRR1)
99 addi r3,r1,STACK_FRAME_OVERHEAD
100 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
103 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
105 /* I guess we could implement decrementer, and may have
106 * to someday for timekeeping.
108 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
109 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
110 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
111 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
112 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
113 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
114 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
115 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
116 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
117 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
118 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
119 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
120 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
121 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
122 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
123 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
124 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
125 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
126 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
127 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
128 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
129 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
130 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
132 .globl _end_of_vectors
139 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
140 * address specified by the BPTR
143 #ifdef CONFIG_SYS_RAMBOOT
144 /* disable everything */
151 /* Invalidate BATs */
154 /* Invalidate all of TLB before MMU turn on */
159 /* init the L2 cache */
161 ori r3, r3, L2_INIT@l
163 /* invalidate the L2 cache */
164 bl l2cache_invalidate
169 * Calculate absolute address in FLASH and jump there
170 *------------------------------------------------------*/
171 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
172 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
173 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
178 /* let the C-code set up the rest */
180 /* Be careful to keep code relocatable ! */
181 /*------------------------------------------------------*/
182 /* perform low-level init */
184 /* enable extended addressing */
191 * Cache must be enabled here for stack-in-cache trick.
192 * This means we need to enable the BATS.
193 * Cache should be turned on after BATs, since by default
194 * everything is write-through.
197 /* enable address translation */
199 ori r5, r5, (MSR_IR | MSR_DR)
200 lis r3,addr_trans_enabled@h
201 ori r3, r3, addr_trans_enabled@l
207 /* enable and invalidate the data cache */
208 /* bl l1dcache_enable */
216 #ifdef CONFIG_SYS_INIT_RAM_LOCK
221 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
225 /* set up the stack pointer in our newly created
227 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
228 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
230 li r0, 0 /* Make room for stack frame header and */
231 stwu r0, -4(r1) /* clear final stack frame so that */
232 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
234 GET_GOT /* initialize GOT access */
236 /* run low-level CPU init code (from Flash) */
242 /* Load PX_AUX register address in r4 */
245 /* Load contents of PX_AUX in r3 bits 24 to 31*/
248 /* Mask and obtain the bit in r3 */
249 rlwinm. r3, r3, 0, 24, 24
250 /* If not zero, jump and continue with u-boot */
253 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
255 /* Set the MSB of the register value */
257 /* Write value in r3 back to PX_AUX */
260 /* Get the address to jump to in r3*/
261 lis r3, CONFIG_SYS_DIAG_ADDR@h
262 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
264 /* Load the LR with the branch address */
267 /* Branch to diagnostic */
273 /* bl l2cache_enable */
275 /* run 1st part of board init code (from Flash) */
279 /* NOTREACHED - board_init_f() does not return */
281 .globl invalidate_bats
285 /* invalidate BATs */
309 #define CONFIG_BAT_PAIR(n) \
310 lis r4, CONFIG_SYS_IBAT##n##L@h; \
311 ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
312 lis r3, CONFIG_SYS_IBAT##n##U@h; \
313 ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \
314 mtspr IBAT##n##L, r4; \
315 mtspr IBAT##n##U, r3; \
316 lis r4, CONFIG_SYS_DBAT##n##L@h; \
317 ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \
318 lis r3, CONFIG_SYS_DBAT##n##U@h; \
319 ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \
320 mtspr DBAT##n##L, r4; \
321 mtspr DBAT##n##U, r3;
326 * Set up the final BAT registers now that setup is done.
329 * 1) Address translation is enabled upon entry
330 * 2) The boot rom is still accessible via 1:1 translation
338 * When we disable address translation, we will get 1:1 (VA==PA)
339 * translation. The only place we know for sure is safe for that is
340 * the bootrom where we originally started out. Pop back into there.
342 lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
343 ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
344 addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
346 /* disable address translation */
348 rlwinm r3, r3, 0, 28, 25
354 #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
355 && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
369 /* Turn translation back on and return */
371 ori r3, r3, (MSR_IR | MSR_DR)
379 * Set up bats needed early on - this is usually the BAT for the
380 * stack-in-cache, the Flash, and CCSR space
385 lis r4, CONFIG_SYS_IBAT3L@h
386 ori r4, r4, CONFIG_SYS_IBAT3L@l
387 lis r3, CONFIG_SYS_IBAT3U@h
388 ori r3, r3, CONFIG_SYS_IBAT3U@l
394 lis r4, CONFIG_SYS_DBAT3L@h
395 ori r4, r4, CONFIG_SYS_DBAT3L@l
396 lis r3, CONFIG_SYS_DBAT3U@h
397 ori r3, r3, CONFIG_SYS_DBAT3U@l
403 lis r4, CONFIG_SYS_IBAT5L@h
404 ori r4, r4, CONFIG_SYS_IBAT5L@l
405 lis r3, CONFIG_SYS_IBAT5U@h
406 ori r3, r3, CONFIG_SYS_IBAT5U@l
412 lis r4, CONFIG_SYS_DBAT5L@h
413 ori r4, r4, CONFIG_SYS_DBAT5L@l
414 lis r3, CONFIG_SYS_DBAT5U@h
415 ori r3, r3, CONFIG_SYS_DBAT5U@l
421 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
422 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
423 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
424 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
430 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
431 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
432 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
433 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
438 #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
440 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
441 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
442 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
443 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
449 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
450 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
451 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
452 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
472 .globl disable_addr_trans
474 /* disable address translation */
477 andi. r0, r3, (MSR_IR | MSR_DR)
485 * This code finishes saving the registers to the exception frame
486 * and jumps to the appropriate handler for the exception.
487 * Register r21 is pointer into trap frame, r1 has new stack pointer.
489 .globl transfer_to_handler
500 andi. r24,r23,0x3f00 /* get vector offset */
504 mtspr SPRG2,r22 /* r1 is now kernel sp */
505 lwz r24,0(r23) /* virtual address of handler */
506 lwz r23,4(r23) /* where to go when done */
511 rfi /* jump to handler, enable MMU */
514 mfmsr r28 /* Disable interrupts */
518 SYNC /* Some chip revs need this... */
533 lwz r2,_NIP(r1) /* Restore environment */
560 * Description: Input 8 bits
569 * Description: Output 8 bits
578 * Description: Output 16 bits
587 * Description: Byte reverse and output 16 bits
596 * Description: Output 32 bits
605 * Description: Byte reverse and output 32 bits
614 * Description: Input 16 bits
623 * Description: Input 16 bits and byte reverse
632 * Description: Input 32 bits
641 * Description: Input 32 bits and byte reverse
649 * void relocate_code (addr_sp, gd, addr_moni)
651 * This "function" does not return, instead it continues in RAM
652 * after relocating the monitor code.
656 * r5 = length in bytes
662 mr r1, r3 /* Set new stack pointer */
663 mr r9, r4 /* Save copy of Global Data pointer */
664 mr r10, r5 /* Save copy of Destination Address */
667 mr r3, r5 /* Destination Address */
668 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
669 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
670 lwz r5, GOT(__init_end)
672 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
677 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
683 /* First our own GOT */
685 /* then the one used by the C code */
694 beq cr1,4f /* In place copy is not necessary */
695 beq 7f /* Protect against 0 count */
713 * Now flush the cache: note that we must start from a cache aligned
714 * address. Otherwise we might miss one cache line.
718 beq 7f /* Always flush prefetch queue in any case */
726 sync /* Wait for all dcbst to complete on bus */
732 7: sync /* Wait for all icbi to complete on bus */
736 * We are done. Do not return, instead branch to second part of board
737 * initialization, now running from RAM.
739 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
745 * Relocation Function, r12 point to got2+0x8000
747 * Adjust got2 pointers, no need to check for 0, this code
748 * already puts a few entries in the table.
750 li r0,__got2_entries@sectoff@l
751 la r3,GOT(_GOT2_TABLE_)
752 lwz r11,GOT(_GOT2_TABLE_)
764 * Now adjust the fixups and the pointers to the fixups
765 * in case we need to move ourselves again.
767 li r0,__fixup_entries@sectoff@l
768 lwz r3,GOT(_FIXUP_TABLE_)
784 * Now clear BSS segment
786 lwz r3,GOT(__bss_start)
787 lwz r4,GOT(__bss_end)
799 mr r3, r9 /* Init Date pointer */
800 mr r4, r10 /* Destination Address */
803 /* not reached - end relocate_code */
804 /*-----------------------------------------------------------------------*/
807 * Copy exception vector code to low memory
810 * r7: source address, r8: end address, r9: target address
814 mflr r4 /* save link register */
817 lwz r8, GOT(_end_of_vectors)
819 li r9, 0x100 /* reset vector always at 0x100 */
822 bgelr /* return if r7>=r8 - just in case */
832 * relocate `hdlr' and `int_return' entries
834 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
835 li r8, Alignment - _start + EXC_OFF_SYS_RESET
838 addi r7, r7, 0x100 /* next exception vector */
842 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
845 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
848 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
849 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
852 addi r7, r7, 0x100 /* next exception vector */
856 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
857 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
860 addi r7, r7, 0x100 /* next exception vector */
864 /* enable execptions from RAM vectors */
868 ori r7,r7,MSR_ME /* Enable Machine Check */
871 mtlr r4 /* restore link register */
874 .globl enable_ext_addr
877 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
878 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
884 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
887 /* Special sequence needed to update CCSRBAR itself */
888 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
889 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
891 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
892 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
894 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
896 stw r5, 0(r4) /* Store physical value of CCSR */
899 lis r5, CONFIG_SYS_TEXT_BASE@h
900 ori r5,r5,CONFIG_SYS_TEXT_BASE@l
904 /* Use VA of CCSR to do read */
905 lis r3, CONFIG_SYS_CCSRBAR@h
906 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
912 #ifdef CONFIG_SYS_INIT_RAM_LOCK
914 /* Allocate Initial RAM in data cache.
916 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
917 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
918 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
919 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
926 /* Lock the data cache */
935 /* Lock the first way of the data cache */
938 #if defined(CONFIG_ALTIVEC)
948 .globl unlock_ram_in_cache
950 /* invalidate the INIT_RAM section */
951 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
952 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
953 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
954 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
959 sync /* Wait for all icbi to complete on bus */
962 /* Unlock the data cache and invalidate it */
974 /* Unlock the first way of the data cache */
978 #ifdef CONFIG_ALTIVEC