1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2011 Freescale Semiconductor.
4 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
7 /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
10 * The processor starts at 0xfff00100 and the code is executed
11 * from flash. The code is organized to be at an other address
12 * in memory, but as long we don't jump around before relocating.
13 * board_init lies at a quite high address and when the cpu has
14 * jumped there, everything is ok.
16 #include <asm-offsets.h>
21 #include <ppc_asm.tmpl>
24 #include <asm/cache.h>
26 #include <asm/u-boot.h>
29 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
33 * Set up GOT: Global Offset Table
35 * Use r12 to access the GOT
38 GOT_ENTRY(_GOT2_TABLE_)
39 GOT_ENTRY(_FIXUP_TABLE_)
42 GOT_ENTRY(_start_of_vectors)
43 GOT_ENTRY(_end_of_vectors)
44 GOT_ENTRY(transfer_to_handler)
48 GOT_ENTRY(__bss_start)
52 * r3 - 1st arg to board_init(): IMMP pointer
53 * r4 - 2nd arg to board_init(): boot flag
56 .long 0x27051956 /* U-Boot Magic Number */
59 .ascii U_BOOT_VERSION_STRING, "\0"
66 /* the boot code is located below the exception table */
68 .globl _start_of_vectors
72 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
74 /* Data Storage exception. */
75 STD_EXCEPTION(0x300, DataStorage, UnknownException)
77 /* Instruction Storage exception. */
78 STD_EXCEPTION(0x400, InstStorage, UnknownException)
80 /* External Interrupt exception. */
81 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
83 /* Alignment exception. */
86 EXCEPTION_PROLOG(SRR0, SRR1)
91 addi r3,r1,STACK_FRAME_OVERHEAD
92 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
94 /* Program check exception */
97 EXCEPTION_PROLOG(SRR0, SRR1)
98 addi r3,r1,STACK_FRAME_OVERHEAD
99 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
102 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
104 /* I guess we could implement decrementer, and may have
105 * to someday for timekeeping.
107 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
108 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
109 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
110 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
111 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
112 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
113 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
114 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
115 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
116 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
117 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
118 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
119 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
120 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
121 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
122 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
123 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
124 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
125 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
126 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
127 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
128 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
129 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
131 .globl _end_of_vectors
138 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
139 * address specified by the BPTR
142 #ifdef CONFIG_SYS_RAMBOOT
143 /* disable everything */
150 /* Invalidate BATs */
153 /* Invalidate all of TLB before MMU turn on */
158 /* init the L2 cache */
160 ori r3, r3, L2_INIT@l
162 /* invalidate the L2 cache */
163 bl l2cache_invalidate
168 * Calculate absolute address in FLASH and jump there
169 *------------------------------------------------------*/
170 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
171 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
172 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
177 /* let the C-code set up the rest */
179 /* Be careful to keep code relocatable ! */
180 /*------------------------------------------------------*/
181 /* perform low-level init */
183 /* enable extended addressing */
190 * Cache must be enabled here for stack-in-cache trick.
191 * This means we need to enable the BATS.
192 * Cache should be turned on after BATs, since by default
193 * everything is write-through.
196 /* enable address translation */
198 ori r5, r5, (MSR_IR | MSR_DR)
199 lis r3,addr_trans_enabled@h
200 ori r3, r3, addr_trans_enabled@l
206 /* enable and invalidate the data cache */
207 /* bl l1dcache_enable */
215 #ifdef CONFIG_SYS_INIT_RAM_LOCK
220 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
224 /* set up the stack pointer in our newly created
226 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
227 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
229 li r0, 0 /* Make room for stack frame header and */
230 stwu r0, -4(r1) /* clear final stack frame so that */
231 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
233 GET_GOT /* initialize GOT access */
235 /* run low-level CPU init code (from Flash) */
241 /* Load PX_AUX register address in r4 */
244 /* Load contents of PX_AUX in r3 bits 24 to 31*/
247 /* Mask and obtain the bit in r3 */
248 rlwinm. r3, r3, 0, 24, 24
249 /* If not zero, jump and continue with u-boot */
252 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
254 /* Set the MSB of the register value */
256 /* Write value in r3 back to PX_AUX */
259 /* Get the address to jump to in r3*/
260 lis r3, CONFIG_SYS_DIAG_ADDR@h
261 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
263 /* Load the LR with the branch address */
266 /* Branch to diagnostic */
272 /* bl l2cache_enable */
274 /* run 1st part of board init code (from Flash) */
275 li r3, 0 /* clear boot_flag for calling board_init_f */
279 /* NOTREACHED - board_init_f() does not return */
281 .globl invalidate_bats
285 /* invalidate BATs */
309 #define CONFIG_BAT_PAIR(n) \
310 lis r4, CONFIG_SYS_IBAT##n##L@h; \
311 ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
312 lis r3, CONFIG_SYS_IBAT##n##U@h; \
313 ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \
314 mtspr IBAT##n##L, r4; \
315 mtspr IBAT##n##U, r3; \
316 lis r4, CONFIG_SYS_DBAT##n##L@h; \
317 ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \
318 lis r3, CONFIG_SYS_DBAT##n##U@h; \
319 ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \
320 mtspr DBAT##n##L, r4; \
321 mtspr DBAT##n##U, r3;
326 * Set up the final BAT registers now that setup is done.
329 * 1) Address translation is enabled upon entry
330 * 2) The boot rom is still accessible via 1:1 translation
338 * When we disable address translation, we will get 1:1 (VA==PA)
339 * translation. The only place we know for sure is safe for that is
340 * the bootrom where we originally started out. Pop back into there.
342 lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
343 ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
344 addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
346 /* disable address translation */
348 rlwinm r3, r3, 0, 28, 25
354 #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
355 && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
369 /* Turn translation back on and return */
371 ori r3, r3, (MSR_IR | MSR_DR)
379 * Set up bats needed early on - this is usually the BAT for the
380 * stack-in-cache, the Flash, and CCSR space
385 lis r4, CONFIG_SYS_IBAT3L@h
386 ori r4, r4, CONFIG_SYS_IBAT3L@l
387 lis r3, CONFIG_SYS_IBAT3U@h
388 ori r3, r3, CONFIG_SYS_IBAT3U@l
394 lis r4, CONFIG_SYS_DBAT3L@h
395 ori r4, r4, CONFIG_SYS_DBAT3L@l
396 lis r3, CONFIG_SYS_DBAT3U@h
397 ori r3, r3, CONFIG_SYS_DBAT3U@l
403 lis r4, CONFIG_SYS_IBAT5L@h
404 ori r4, r4, CONFIG_SYS_IBAT5L@l
405 lis r3, CONFIG_SYS_IBAT5U@h
406 ori r3, r3, CONFIG_SYS_IBAT5U@l
412 lis r4, CONFIG_SYS_DBAT5L@h
413 ori r4, r4, CONFIG_SYS_DBAT5L@l
414 lis r3, CONFIG_SYS_DBAT5U@h
415 ori r3, r3, CONFIG_SYS_DBAT5U@l
421 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
422 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
423 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
424 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
430 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
431 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
432 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
433 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
438 #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
440 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
441 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
442 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
443 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
449 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
450 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
451 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
452 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
472 .globl disable_addr_trans
474 /* disable address translation */
477 andi. r0, r3, (MSR_IR | MSR_DR)
485 * This code finishes saving the registers to the exception frame
486 * and jumps to the appropriate handler for the exception.
487 * Register r21 is pointer into trap frame, r1 has new stack pointer.
489 .globl transfer_to_handler
500 andi. r24,r23,0x3f00 /* get vector offset */
504 mtspr SPRG2,r22 /* r1 is now kernel sp */
505 lwz r24,0(r23) /* virtual address of handler */
506 lwz r23,4(r23) /* where to go when done */
511 rfi /* jump to handler, enable MMU */
514 mfmsr r28 /* Disable interrupts */
518 SYNC /* Some chip revs need this... */
533 lwz r2,_NIP(r1) /* Restore environment */
550 * Description: Input 8 bits
559 * Description: Output 8 bits
568 * Description: Output 16 bits
577 * Description: Byte reverse and output 16 bits
586 * Description: Output 32 bits
595 * Description: Byte reverse and output 32 bits
604 * Description: Input 16 bits
613 * Description: Input 16 bits and byte reverse
622 * Description: Input 32 bits
631 * Description: Input 32 bits and byte reverse
639 * void relocate_code (addr_sp, gd, addr_moni)
641 * This "function" does not return, instead it continues in RAM
642 * after relocating the monitor code.
646 * r5 = length in bytes
652 mr r1, r3 /* Set new stack pointer */
653 mr r9, r4 /* Save copy of Global Data pointer */
654 mr r10, r5 /* Save copy of Destination Address */
657 mr r3, r5 /* Destination Address */
658 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
659 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
660 lwz r5, GOT(__init_end)
662 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
667 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
673 /* First our own GOT */
675 /* then the one used by the C code */
684 beq cr1,4f /* In place copy is not necessary */
685 beq 7f /* Protect against 0 count */
703 * Now flush the cache: note that we must start from a cache aligned
704 * address. Otherwise we might miss one cache line.
708 beq 7f /* Always flush prefetch queue in any case */
716 sync /* Wait for all dcbst to complete on bus */
722 7: sync /* Wait for all icbi to complete on bus */
726 * We are done. Do not return, instead branch to second part of board
727 * initialization, now running from RAM.
729 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
735 * Relocation Function, r12 point to got2+0x8000
737 * Adjust got2 pointers, no need to check for 0, this code
738 * already puts a few entries in the table.
740 li r0,__got2_entries@sectoff@l
741 la r3,GOT(_GOT2_TABLE_)
742 lwz r11,GOT(_GOT2_TABLE_)
754 * Now adjust the fixups and the pointers to the fixups
755 * in case we need to move ourselves again.
757 li r0,__fixup_entries@sectoff@l
758 lwz r3,GOT(_FIXUP_TABLE_)
774 * Now clear BSS segment
776 lwz r3,GOT(__bss_start)
777 lwz r4,GOT(__bss_end)
789 mr r3, r9 /* Init Date pointer */
790 mr r4, r10 /* Destination Address */
793 /* not reached - end relocate_code */
794 /*-----------------------------------------------------------------------*/
797 * Copy exception vector code to low memory
800 * r7: source address, r8: end address, r9: target address
804 mflr r4 /* save link register */
807 lwz r8, GOT(_end_of_vectors)
809 li r9, 0x100 /* reset vector always at 0x100 */
812 bgelr /* return if r7>=r8 - just in case */
822 * relocate `hdlr' and `int_return' entries
824 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
825 li r8, Alignment - _start + EXC_OFF_SYS_RESET
828 addi r7, r7, 0x100 /* next exception vector */
832 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
835 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
838 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
839 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
842 addi r7, r7, 0x100 /* next exception vector */
846 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
847 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
850 addi r7, r7, 0x100 /* next exception vector */
854 /* enable execptions from RAM vectors */
858 ori r7,r7,MSR_ME /* Enable Machine Check */
861 mtlr r4 /* restore link register */
864 .globl enable_ext_addr
867 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
868 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
874 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
877 /* Special sequence needed to update CCSRBAR itself */
878 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
879 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
881 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
882 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
884 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
886 stw r5, 0(r4) /* Store physical value of CCSR */
889 lis r5, CONFIG_SYS_TEXT_BASE@h
890 ori r5,r5,CONFIG_SYS_TEXT_BASE@l
894 /* Use VA of CCSR to do read */
895 lis r3, CONFIG_SYS_CCSRBAR@h
896 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
902 #ifdef CONFIG_SYS_INIT_RAM_LOCK
904 /* Allocate Initial RAM in data cache.
906 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
907 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
908 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
909 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
916 /* Lock the data cache */
925 /* Lock the first way of the data cache */
928 #if defined(CONFIG_ALTIVEC)
938 .globl unlock_ram_in_cache
940 /* invalidate the INIT_RAM section */
941 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
942 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
943 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
944 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
949 sync /* Wait for all icbi to complete on bus */
952 /* Unlock the data cache and invalidate it */
964 /* Unlock the first way of the data cache */
968 #ifdef CONFIG_ALTIVEC