1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2008 Freescale Semiconductor.
4 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
9 #include <ppc_asm.tmpl>
12 #include <asm/cache.h>
15 /* If this is a multi-cpu system then we need to handle the
16 * 2nd cpu. The assumption is that the 2nd cpu is being
17 * held in boot holdoff mode until the 1st cpu unlocks it
18 * from Linux. We'll do some basic cpu init and then pass
19 * it to the Linux Reset Vector.
20 * Sri: Much of this initialization is not required. Linux
21 * rewrites the bats, and the sprs and also enables the L1 cache.
23 * Core 0 must copy this to a 1M aligned region and set BPTR
27 .globl __secondary_start_page
28 __secondary_start_page:
29 .space 0x100 /* space over to reset vector loc */
57 /* enable extended addressing */
59 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
60 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
66 /* init the L2 cache */
67 addis r3, r0, L2_INIT@h
74 /* invalidate the L2 cache */
76 rlwinm. r3, r3, 0, 0, 0
80 rlwinm r3, r3, 0, 1, 31
89 oris r3, r3, L2CR_L2I@h
94 andis. r3, r3, L2CR_L2I@h
99 /* enable and invalidate the data cache */
101 li r5, HID0_DCFI|HID0_DLOCK
103 mtspr HID0, r3 /* no invalidate, unlock */
105 ori r5, r3, HID0_DCFI
106 mtspr HID0, r5 /* enable + invalidate */
107 mtspr HID0, r3 /* enable */
112 ori r3, r3, L2_ENABLE@l
118 /* enable and invalidate the instruction cache*/
120 li r5, HID0_ICFI|HID0_ILOCK
123 ori r5, r3, HID0_ICFI
136 /* MCP|SYNCBE|ABE in HID1 */
144 lis r3, CONFIG_LINUX_RESET_VEC@h
145 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
149 /* Never Returns, Running in Linux Now */