2 * Copyright 2004, 2007, 2008 Freescale Semiconductor.
3 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <ppc_asm.tmpl>
30 #include <asm/cache.h>
33 /* If this is a multi-cpu system then we need to handle the
34 * 2nd cpu. The assumption is that the 2nd cpu is being
35 * held in boot holdoff mode until the 1st cpu unlocks it
36 * from Linux. We'll do some basic cpu init and then pass
37 * it to the Linux Reset Vector.
38 * Sri: Much of this initialization is not required. Linux
39 * rewrites the bats, and the sprs and also enables the L1 cache.
41 * Core 0 must copy this to a 1M aligned region and set BPTR
45 .globl __secondary_start_page
46 __secondary_start_page:
47 .space 0x100 /* space over to reset vector loc */
75 /* enable extended addressing */
77 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
78 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
84 /* init the L2 cache */
85 addis r3, r0, L2_INIT@h
92 /* invalidate the L2 cache */
94 rlwinm. r3, r3, 0, 0, 0
98 rlwinm r3, r3, 0, 1, 31
100 #ifdef CONFIG_ALTIVEC
107 oris r3, r3, L2CR_L2I@h
112 andis. r3, r3, L2CR_L2I@h
117 /* enable and invalidate the data cache */
119 li r5, HID0_DCFI|HID0_DLOCK
121 mtspr HID0, r3 /* no invalidate, unlock */
123 ori r5, r3, HID0_DCFI
124 mtspr HID0, r5 /* enable + invalidate */
125 mtspr HID0, r3 /* enable */
130 ori r3, r3, L2_ENABLE@l
136 /* enable and invalidate the instruction cache*/
138 li r5, HID0_ICFI|HID0_ILOCK
141 ori r5, r3, HID0_ICFI
154 /* MCP|SYNCBE|ABE in HID1 */
162 lis r3, CONFIG_LINUX_RESET_VEC@h
163 ori r3, r3, CONFIG_LINUX_RESET_VEC@l
167 /* Never Returns, Running in Linux Now */