1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 #include <asm/processor.h>
14 DECLARE_GLOBAL_DATA_PTR;
18 /* dummy function so common/cmd_mp.c will build
19 * should be implemented in the future, when cpu_release()
20 * is supported. Be aware there may be a similiar bug
21 * as exists on MPC85xx w/its PIC having a timing window
22 * associated to resetting the core */
26 int cpu_status(u32 nr)
28 /* dummy function so common/cmd_mp.c will build */
32 int cpu_disable(u32 nr)
34 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
35 volatile ccsr_gur_t *gur = &immap->im_gur;
39 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
42 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
45 printf("Invalid cpu number for disable %d\n", nr);
52 int is_core_disabled(int nr) {
53 immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
54 ccsr_gur_t *gur = &immap->im_gur;
55 u32 devdisr = in_be32(&gur->devdisr);
59 return (devdisr & MPC86xx_DEVDISR_CPU0);
61 return (devdisr & MPC86xx_DEVDISR_CPU1);
63 printf("Invalid cpu number for disable %d\n", nr);
69 int cpu_release(u32 nr, int argc, char * const argv[])
71 /* dummy function so common/cmd_mp.c will build
72 * should be implemented in the future */
76 u32 determine_mp_bootpg(unsigned int *pagesize)
81 /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
82 if ((u64)gd->ram_size > 0xfffff000)
85 return (gd->ram_size - (1024 * 1024));
88 void cpu_mp_lmb_reserve(struct lmb *lmb)
90 u32 bootpg = determine_mp_bootpg(NULL);
92 /* tell u-boot we stole a page */
93 lmb_reserve(lmb, bootpg, 4096);
97 * Copy the code for other cpus to execute into an
98 * aligned location accessible via BPTR
102 extern ulong __secondary_start_page;
103 ulong fixup = (ulong)&__secondary_start_page;
104 u32 bootpg = determine_mp_bootpg(NULL);
107 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
108 /* We're not covered by the DDR mapping, set up BAT */
109 write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
111 bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
112 bootpg_va = CONFIG_SYS_SCRATCH_VA;
117 memcpy((void *)bootpg_va, (void *)fixup, 4096);
118 flush_cache(bootpg_va, 4096);
120 /* remove the temporary BAT mapping */
121 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
122 write_bat(DBAT7, 0, 0);
124 /* If the physical location of bootpg is not at fff00000, set BPTR */
125 if (bootpg != 0xfff00000)
126 out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |