2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
35 /* dummy function so common/cmd_mp.c will build
36 * should be implemented in the future, when cpu_release()
37 * is supported. Be aware there may be a similiar bug
38 * as exists on MPC85xx w/its PIC having a timing window
39 * associated to resetting the core */
43 int cpu_status(int nr)
45 /* dummy function so common/cmd_mp.c will build */
49 int cpu_disable(int nr)
51 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
52 volatile ccsr_gur_t *gur = &immap->im_gur;
56 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
59 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
62 printf("Invalid cpu number for disable %d\n", nr);
69 int is_core_disabled(int nr) {
70 immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
71 ccsr_gur_t *gur = &immap->im_gur;
72 u32 devdisr = in_be32(&gur->devdisr);
76 return (devdisr & MPC86xx_DEVDISR_CPU0);
78 return (devdisr & MPC86xx_DEVDISR_CPU1);
80 printf("Invalid cpu number for disable %d\n", nr);
86 int cpu_release(int nr, int argc, char * const argv[])
88 /* dummy function so common/cmd_mp.c will build
89 * should be implemented in the future */
93 u32 determine_mp_bootpg(unsigned int *pagesize)
98 /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
99 if ((u64)gd->ram_size > 0xfffff000)
102 return (gd->ram_size - (1024 * 1024));
105 void cpu_mp_lmb_reserve(struct lmb *lmb)
107 u32 bootpg = determine_mp_bootpg(NULL);
109 /* tell u-boot we stole a page */
110 lmb_reserve(lmb, bootpg, 4096);
114 * Copy the code for other cpus to execute into an
115 * aligned location accessible via BPTR
119 extern ulong __secondary_start_page;
120 ulong fixup = (ulong)&__secondary_start_page;
121 u32 bootpg = determine_mp_bootpg(NULL);
124 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
125 /* We're not covered by the DDR mapping, set up BAT */
126 write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
128 bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
129 bootpg_va = CONFIG_SYS_SCRATCH_VA;
134 memcpy((void *)bootpg_va, (void *)fixup, 4096);
135 flush_cache(bootpg_va, 4096);
137 /* remove the temporary BAT mapping */
138 if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
139 write_bat(DBAT7, 0, 0);
141 /* If the physical location of bootpg is not at fff00000, set BPTR */
142 if (bootpg != 0xfff00000)
143 out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |