2 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
31 #include <asm/fsl_law.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 * Default board reset function
43 void board_reset(void) __attribute__((weak, alias("__board_reset")));
52 char buf1[32], buf2[32];
53 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
54 volatile ccsr_gur_t *gur = &immap->im_gur;
56 uint msscr0 = mfspr(MSSCR0);
62 if (cpu_numcores() > 1) {
64 puts("Unicore software on multiprocessor system!!\n"
65 "To enable mutlticore build define CONFIG_MP\n");
74 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
78 major = PVR_E600_MAJ(pvr);
79 minor = PVR_E600_MIN(pvr);
81 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
82 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
83 puts("\n Core1Translation Enabled");
84 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
86 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
88 get_sys_info(&sysinfo);
90 puts("Clock Configuration:\n");
91 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
92 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
93 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
94 strmhz(buf1, sysinfo.freqSystemBus / 2),
95 strmhz(buf2, sysinfo.freqSystemBus));
97 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
98 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
100 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
101 sysinfo.freqLocalBus);
104 puts("L1: D-cache 32 KB enabled\n");
105 puts(" I-cache 32 KB enabled\n");
108 if (get_l2cr() & 0x80000000) {
109 #if defined(CONFIG_MPC8610)
111 #elif defined(CONFIG_MPC8641)
114 puts(" KB enabled\n");
123 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
125 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
126 volatile ccsr_gur_t *gur = &immap->im_gur;
128 /* Attempt board-specific reset */
131 /* Next try asserting HRESET_REQ */
132 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
142 * Get timebase clock frequency
149 get_sys_info(&sys_info);
150 return (sys_info.freqSystemBus + 3L) / 4L;
154 #if defined(CONFIG_WATCHDOG)
158 #if defined(CONFIG_MPC8610)
160 * This actually feed the hard enabled watchdog.
162 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
163 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
164 volatile ccsr_gur_t *gur = &immap->im_gur;
165 u32 tmp = gur->pordevsr;
173 #endif /* CONFIG_WATCHDOG */
176 * Print out the state of various machine registers.
177 * Currently prints out LAWs, BR0/OR0, and BATs
179 void mpc86xx_reginfo(void)
187 * Set the DDR BATs to reflect the actual size of DDR.
189 * dram_size is the actual size of DDR, in bytes
191 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
192 * are using a single BAT to cover DDR.
194 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
195 * is not defined) then we might have a situation where U-Boot will attempt
196 * to relocated itself outside of the region mapped by DBAT0.
197 * This will cause a machine check.
199 * Currently we are limited to power of two sized DDR since we only use a
200 * single bat. If a non-power of two size is used that is less than
201 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
204 void setup_ddr_bat(phys_addr_t dram_size)
206 unsigned long batu, bl;
208 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
210 if (BATU_SIZE(bl) != dram_size) {
211 u64 sz = (u64)dram_size - BATU_SIZE(bl);
212 print_size(sz, " left unmapped\n");
215 batu = bl | BATU_VS | BATU_VP;
216 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
217 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);