2 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
31 #include <asm/fsl_law.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 * Default board reset function
43 void board_reset(void) __attribute__((weak, alias("__board_reset")));
53 char buf1[32], buf2[32];
54 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
55 volatile ccsr_gur_t *gur = &immap->im_gur;
57 uint msscr0 = mfspr(MSSCR0);
60 ver = SVR_SOC_VER(svr);
64 if (cpu_numcores() > 1) {
66 puts("Unicore software on multiprocessor system!!\n"
67 "To enable mutlticore build define CONFIG_MP\n");
76 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
80 ver = PVR_E600_VER(pvr);
81 major = PVR_E600_MAJ(pvr);
82 minor = PVR_E600_MIN(pvr);
84 printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
85 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
86 puts("\n Core1Translation Enabled");
87 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
89 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
91 get_sys_info(&sysinfo);
93 puts("Clock Configuration:\n");
94 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
95 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
96 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
97 strmhz(buf1, sysinfo.freqSystemBus / 2),
98 strmhz(buf2, sysinfo.freqSystemBus));
100 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
101 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
103 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
104 sysinfo.freqLocalBus);
107 puts("L1: D-cache 32 KB enabled\n");
108 puts(" I-cache 32 KB enabled\n");
111 if (get_l2cr() & 0x80000000) {
112 #if defined(CONFIG_MPC8610)
114 #elif defined(CONFIG_MPC8641)
117 puts(" KB enabled\n");
127 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
129 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
130 volatile ccsr_gur_t *gur = &immap->im_gur;
132 /* Attempt board-specific reset */
135 /* Next try asserting HRESET_REQ */
136 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
144 * Get timebase clock frequency
151 get_sys_info(&sys_info);
152 return (sys_info.freqSystemBus + 3L) / 4L;
156 #if defined(CONFIG_WATCHDOG)
160 #if defined(CONFIG_MPC8610)
162 * This actually feed the hard enabled watchdog.
164 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
165 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
166 volatile ccsr_gur_t *gur = &immap->im_gur;
167 u32 tmp = gur->pordevsr;
175 #endif /* CONFIG_WATCHDOG */
178 * Print out the state of various machine registers.
179 * Currently prints out LAWs, BR0/OR0, and BATs
181 void mpc86xx_reginfo(void)
183 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
184 ccsr_lbc_t *lbc = &immap->im_lbc;
189 printf ("Local Bus Controller Registers\n"
190 "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
191 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
192 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
193 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
194 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
195 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
196 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
197 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
202 * Set the DDR BATs to reflect the actual size of DDR.
204 * dram_size is the actual size of DDR, in bytes
206 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
207 * are using a single BAT to cover DDR.
209 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
210 * is not defined) then we might have a situation where U-Boot will attempt
211 * to relocated itself outside of the region mapped by DBAT0.
212 * This will cause a machine check.
214 * Currently we are limited to power of two sized DDR since we only use a
215 * single bat. If a non-power of two size is used that is less than
216 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
219 void setup_ddr_bat(phys_addr_t dram_size)
221 unsigned long batu, bl;
223 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
225 if (BATU_SIZE(bl) != dram_size) {
226 u64 sz = (u64)dram_size - BATU_SIZE(bl);
227 print_size(sz, " left unmapped\n");
230 batu = bl | BATU_VS | BATU_VP;
231 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
232 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);