2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 #ifdef CONFIG_ADDR_MAP
17 #include <linux/log2.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 void invalidate_tlb(u8 tlb)
29 __weak void init_tlbs(void)
33 for (i = 0; i < num_tlb_entries; i++) {
34 write_tlb(tlb_table[i].mas0,
44 #if !defined(CONFIG_NAND_SPL) && \
45 (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
46 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
51 mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
52 asm volatile("tlbre;isync");
55 *valid = (_mas1 & MAS1_VALID);
56 *tsize = (_mas1 >> 7) & 0x1f;
57 *epn = mfspr(MAS2) & MAS2_EPN;
58 *rpn = mfspr(MAS3) & MAS3_RPN;
59 #ifdef CONFIG_ENABLE_36BIT_PHYS
60 *rpn |= ((u64)mfspr(MAS7)) << 32;
64 void print_tlbcam(void)
67 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
69 /* walk all the entries */
70 printf("TLBCAM entries\n");
71 for (i = 0; i < num_cam; i++) {
76 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
77 printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
78 i, (valid == 0) ? 0 : 1, (unsigned int)epn,
79 (unsigned long long)rpn);
80 print_size(TSIZE_TO_BYTES(tsize), "\n");
84 static inline void use_tlb_cam(u8 idx)
89 gd->arch.used_tlb_cams[i] |= (1 << bit);
92 static inline void free_tlb_cam(u8 idx)
97 gd->arch.used_tlb_cams[i] &= ~(1 << bit);
100 void init_used_tlb_cams(void)
103 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
105 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
106 gd->arch.used_tlb_cams[i] = 0;
108 /* walk all the entries */
109 for (i = 0; i < num_cam; i++) {
110 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
111 asm volatile("tlbre;isync");
112 if (mfspr(MAS1) & MAS1_VALID)
117 int find_free_tlbcam(void)
122 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
123 idx = ffz(gd->arch.used_tlb_cams[i]);
131 if (idx >= CONFIG_SYS_NUM_TLBCAMS)
137 void set_tlb(u8 tlb, u32 epn, u64 rpn,
139 u8 ts, u8 esel, u8 tsize, u8 iprot)
141 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
146 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
148 printf("%s: bad tsize %d on entry %d at 0x%08x\n",
149 __func__, tsize, tlb, epn);
153 _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
154 _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
155 _mas2 = FSL_BOOKE_MAS2(epn, wimge);
156 _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
157 _mas7 = FSL_BOOKE_MAS7(rpn);
159 write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
161 #ifdef CONFIG_ADDR_MAP
162 if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
163 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
167 void disable_tlb(u8 esel)
169 u32 _mas0, _mas1, _mas2, _mas3;
173 _mas0 = FSL_BOOKE_MAS0(1, esel, 0);
182 #ifdef CONFIG_ENABLE_36BIT_PHYS
185 asm volatile("isync;msync;tlbwe;isync");
187 #ifdef CONFIG_ADDR_MAP
188 if (gd->flags & GD_FLG_RELOC)
189 addrmap_set_entry(0, 0, 0, esel);
193 static void tlbsx (const volatile unsigned *addr)
195 __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
198 /* return -1 if we didn't find anything */
199 int find_tlb_idx(void *addr, u8 tlbsel)
203 /* zero out Search PID, AS */
211 /* we found something, and its in the TLB we expect */
212 if ((MAS1_VALID & _mas1) &&
213 (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
214 return ((_mas0 & MAS0_ESEL_MSK) >> 16);
220 #ifdef CONFIG_ADDR_MAP
221 void init_addr_map(void)
224 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
226 /* walk all the entries */
227 for (i = 0; i < num_cam; i++) {
232 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
233 if (valid & MAS1_VALID)
234 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
241 uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
242 enum tlb_map_type map_type)
245 unsigned int tlb_size;
248 unsigned int max_cam, tsize_mask;
250 if (map_type == TLB_MAP_RAM) {
251 perm = MAS3_SX|MAS3_SW|MAS3_SR;
253 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
254 wimge = CONFIG_SYS_PPC_DDR_WIMGE;
257 perm = MAS3_SW|MAS3_SR;
258 wimge = MAS2_I|MAS2_G;
261 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
262 /* Convert (4^max) kB to (2^max) bytes */
263 max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
266 /* Convert (2^max) kB to (2^max) bytes */
267 max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
271 for (i = 0; size && i < 8; i++) {
272 int tlb_index = find_free_tlbcam();
273 u32 camsize = __ilog2_u64(size) & tsize_mask;
274 u32 align = __ilog2(v_addr) & tsize_mask;
279 if (align == -2) align = max_cam;
283 if (camsize > max_cam)
286 tlb_size = camsize - 10;
288 set_tlb(1, v_addr, p_addr, perm, wimge,
289 0, tlb_index, tlb_size, 1);
291 size -= 1ULL << camsize;
292 v_addr += 1UL << camsize;
293 p_addr += 1UL << camsize;
299 unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
300 unsigned int memsize_in_meg)
302 unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
303 u64 memsize = (u64)memsize_in_meg << 20;
306 size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
307 size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
309 if (size || memsize > CONFIG_MAX_MEM_MAPPED) {
310 print_size(memsize > CONFIG_MAX_MEM_MAPPED ?
311 memsize - CONFIG_MAX_MEM_MAPPED + size : size,
315 return memsize_in_meg;
318 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
321 setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
324 /* Invalidate the DDR TLBs for the requested size */
325 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
327 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
329 u32 tsize, valid, ptr;
332 u64 memsize = (u64)memsize_in_meg << 20;
336 while (ptr < (vstart + memsize)) {
337 ddr_esel = find_tlb_idx((void *)ptr, 1);
338 if (ddr_esel != -1) {
339 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
340 disable_tlb(ddr_esel);
342 ptr += TSIZE_TO_BYTES(tsize);
346 void clear_ddr_tlbs(unsigned int memsize_in_meg)
348 clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);