2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
10 * The processor starts at 0xfffffffc and the code is first executed in the
11 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
15 #include <asm-offsets.h>
20 #include <ppc_asm.tmpl>
23 #include <asm/cache.h>
27 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
29 #if defined(CONFIG_NAND_SPL) || \
30 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
34 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
35 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
40 * Set up GOT: Global Offset Table
42 * Use r12 to access the GOT
45 GOT_ENTRY(_GOT2_TABLE_)
46 GOT_ENTRY(_FIXUP_TABLE_)
50 GOT_ENTRY(_start_of_vectors)
51 GOT_ENTRY(_end_of_vectors)
52 GOT_ENTRY(transfer_to_handler)
57 GOT_ENTRY(__bss_start)
61 * e500 Startup -- after reset only the last 4KB of the effective
62 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
63 * section is located at THIS LAST page and basically does three
64 * things: clear some registers, set up exception tables and
65 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
66 * continue the boot procedure.
68 * Once the boot rom is mapped by TLB entries we can proceed
69 * with normal startup.
77 /* Enable debug exception */
81 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
84 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
88 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
89 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
94 /* Not a supported revision affected by erratum */
98 1: li r27,1 /* Remember for later that we have the erratum */
99 /* Erratum says set bits 55:60 to 001001 */
109 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
112 mfspr r3, SPRN_HDBCR0
114 mtspr SPRN_HDBCR0, r3
118 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
119 /* ISBC uses L2 as stack.
120 * Disable L2 cache here so that u-boot can enable it later
121 * as part of it's normal flow
124 /* Check if L2 is enabled */
125 mfspr r3, SPRN_L2CSR0
127 ori r2, r2, L2CSR0_L2E@l
131 mfspr r3, SPRN_L2CSR0
133 lis r2,(L2CSR0_L2FL)@h
134 ori r2, r2, (L2CSR0_L2FL)@l
141 mfspr r3, SPRN_L2CSR0
145 mfspr r3, SPRN_L2CSR0
147 ori r2, r2, L2CSR0_L2E@l
157 /* clear registers/arrays not reset by hardware */
161 mtspr L1CSR0,r0 /* invalidate d-cache */
162 mtspr L1CSR1,r0 /* invalidate i-cache */
165 mtspr DBSR,r1 /* Clear all valid bits */
168 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
169 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
170 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
172 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
173 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
175 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
176 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
178 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
179 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
181 lis \scratch, \phy_high@h
182 ori \scratch, \scratch, \phy_high@l
190 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
191 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
192 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
194 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
195 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
197 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
198 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
200 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
201 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
203 lis \scratch, \phy_high@h
204 ori \scratch, \scratch, \phy_high@l
212 .macro delete_tlb1_entry esel scratch
213 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
214 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
224 .macro delete_tlb0_entry esel epn wimg scratch
225 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
226 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
230 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
231 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
239 /* Interrupt vectors do not fit in minimal SPL. */
240 #if !defined(MINIMAL_SPL)
241 /* Setup interrupt vectors */
242 lis r1,CONFIG_SYS_MONITOR_BASE@h
245 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
246 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
248 addi r4,r3,CriticalInput - _start + _START_OFFSET
249 mtspr IVOR0,r4 /* 0: Critical input */
250 addi r4,r3,MachineCheck - _start + _START_OFFSET
251 mtspr IVOR1,r4 /* 1: Machine check */
252 addi r4,r3,DataStorage - _start + _START_OFFSET
253 mtspr IVOR2,r4 /* 2: Data storage */
254 addi r4,r3,InstStorage - _start + _START_OFFSET
255 mtspr IVOR3,r4 /* 3: Instruction storage */
256 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
257 mtspr IVOR4,r4 /* 4: External interrupt */
258 addi r4,r3,Alignment - _start + _START_OFFSET
259 mtspr IVOR5,r4 /* 5: Alignment */
260 addi r4,r3,ProgramCheck - _start + _START_OFFSET
261 mtspr IVOR6,r4 /* 6: Program check */
262 addi r4,r3,FPUnavailable - _start + _START_OFFSET
263 mtspr IVOR7,r4 /* 7: floating point unavailable */
264 addi r4,r3,SystemCall - _start + _START_OFFSET
265 mtspr IVOR8,r4 /* 8: System call */
266 /* 9: Auxiliary processor unavailable(unsupported) */
267 addi r4,r3,Decrementer - _start + _START_OFFSET
268 mtspr IVOR10,r4 /* 10: Decrementer */
269 addi r4,r3,IntervalTimer - _start + _START_OFFSET
270 mtspr IVOR11,r4 /* 11: Interval timer */
271 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
272 mtspr IVOR12,r4 /* 12: Watchdog timer */
273 addi r4,r3,DataTLBError - _start + _START_OFFSET
274 mtspr IVOR13,r4 /* 13: Data TLB error */
275 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
276 mtspr IVOR14,r4 /* 14: Instruction TLB error */
277 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
278 mtspr IVOR15,r4 /* 15: Debug */
281 /* Clear and set up some registers. */
284 mtspr DEC,r0 /* prevent dec exceptions */
285 mttbl r0 /* prevent fit & wdt exceptions */
287 mtspr TSR,r1 /* clear all timer exception status */
288 mtspr TCR,r0 /* disable all */
289 mtspr ESR,r0 /* clear exception syndrome register */
290 mtspr MCSR,r0 /* machine check syndrome register */
291 mtxer r0 /* clear integer exception register */
293 #ifdef CONFIG_SYS_BOOK3E_HV
294 mtspr MAS8,r0 /* make sure MAS8 is clear */
297 /* Enable Time Base and Select Time Base Clock */
298 lis r0,HID0_EMCP@h /* Enable machine check */
299 #if defined(CONFIG_ENABLE_36BIT_PHYS)
300 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
302 #ifndef CONFIG_E500MC
303 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
307 #ifndef CONFIG_E500MC
308 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
311 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
313 /* Set MBDD bit also */
314 ori r0, r0, HID1_MBDD@l
319 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
325 /* Enable Branch Prediction */
326 #if defined(CONFIG_BTB)
327 lis r0,BUCSR_ENABLE@h
328 ori r0,r0,BUCSR_ENABLE@l
332 #if defined(CONFIG_SYS_INIT_DBCR)
335 mtspr DBSR,r1 /* Clear all status bits */
336 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
337 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
341 #ifdef CONFIG_MPC8569
342 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
343 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
345 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
346 * use address space which is more than 12bits, and it must be done in
347 * the 4K boot page. So we set this bit here.
350 /* create a temp mapping TLB0[0] for LBCR */
351 create_tlb0_entry 0, \
352 0, BOOKE_PAGESZ_4K, \
353 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
354 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
357 /* Set LBCR register */
358 lis r4,CONFIG_SYS_LBCR_ADDR@h
359 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
361 lis r5,CONFIG_SYS_LBC_LBCR@h
362 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
366 /* invalidate this temp TLB */
367 lis r4,CONFIG_SYS_LBC_ADDR@h
368 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
372 #endif /* CONFIG_MPC8569 */
375 * Search for the TLB that covers the code we're executing, and shrink it
376 * so that it covers only this 4K page. That will ensure that any other
377 * TLB we create won't interfere with it. We assume that the TLB exists,
378 * which is why we don't check the Valid bit of MAS1. We also assume
381 * This is necessary, for example, when booting from the on-chip ROM,
382 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
384 bl nexti /* Find our address */
385 nexti: mflr r1 /* R1 = our PC */
387 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
390 tlbsx 0, r1 /* This must succeed */
392 mfspr r14, MAS0 /* Save ESEL for later */
393 rlwinm r14, r14, 16, 0xfff
395 /* Set the size of the TLB to 4KB */
398 andc r3, r3, r2 /* Clear the TSIZE bits */
399 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
400 oris r3, r3, MAS1_IPROT@h
404 * Set the base address of the TLB to our PC. We assume that
405 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
408 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
410 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
415 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
418 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
419 rlwinm r2, r2, 0, ~MAS2_I
423 mtspr MAS2, r2 /* Set the EPN to our PC base address */
428 mtspr MAS3, r2 /* Set the RPN to our PC base address */
435 * Clear out any other TLB entries that may exist, to avoid conflicts.
436 * Our TLB entry is in r14.
438 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
442 mfspr r4, SPRN_TLB1CFG
443 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
448 rlwinm r5, r3, 16, MAS0_ESEL_MSK
450 beq 2f /* skip the entry we're executing from */
452 oris r5, r5, MAS0_TLBSEL(1)@h
463 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
465 * TLB entry for debuggging in AS1
466 * Create temporary TLB entry in AS0 to handle debug exception
467 * As on debug exception MSR is cleared i.e. Address space is changed
468 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
474 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
475 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
476 * and this window is outside of 4K boot window.
478 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
479 0, BOOKE_PAGESZ_4M, \
480 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
481 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
484 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
485 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
486 0, BOOKE_PAGESZ_1M, \
487 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
488 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
492 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
493 * because "nexti" will resize TLB to 4K
495 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
496 0, BOOKE_PAGESZ_256K, \
497 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
498 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
504 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
505 * location is not where we want it. This typically happens on a 36-bit
506 * system, where we want to move CCSR to near the top of 36-bit address space.
508 * To move CCSR, we create two temporary TLBs, one for the old location, and
509 * another for the new location. On CoreNet systems, we also need to create
510 * a special, temporary LAW.
512 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
513 * long-term TLBs, so we use TLB0 here.
515 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
517 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
518 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
523 * Create a TLB for the new location of CCSR. Register R8 is reserved
524 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
526 lis r8, CONFIG_SYS_CCSRBAR@h
527 ori r8, r8, CONFIG_SYS_CCSRBAR@l
528 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
529 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
530 create_tlb0_entry 0, \
531 0, BOOKE_PAGESZ_4K, \
532 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
533 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
534 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
536 * Create a TLB for the current location of CCSR. Register R9 is reserved
537 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
540 create_tlb0_entry 1, \
541 0, BOOKE_PAGESZ_4K, \
542 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
543 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
544 0, r3 /* The default CCSR address is always a 32-bit number */
548 * We have a TLB for what we think is the current (old) CCSR. Let's
549 * verify that, otherwise we won't be able to move it.
550 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
551 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
554 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
555 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
556 #ifdef CONFIG_FSL_CORENET
557 lwz r1, 4(r9) /* CCSRBARL */
559 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
566 * If the value we read from CCSRBARL is not what we expect, then
567 * enter an infinite loop. This will at least allow a debugger to
568 * halt execution and examine TLBs, etc. There's no point in going
572 bne infinite_debug_loop
574 #ifdef CONFIG_FSL_CORENET
576 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
577 #define LAW_EN 0x80000000
578 #define LAW_SIZE_4K 0xb
579 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
580 #define CCSRAR_C 0x80000000 /* Commit */
584 * On CoreNet systems, we create the temporary LAW using a special LAW
585 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
587 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
588 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
589 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
590 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
591 lis r2, CCSRBAR_LAWAR@h
592 ori r2, r2, CCSRBAR_LAWAR@l
594 stw r0, 0xc00(r9) /* LAWBARH0 */
595 stw r1, 0xc04(r9) /* LAWBARL0 */
597 stw r2, 0xc08(r9) /* LAWAR0 */
600 * Read back from LAWAR to ensure the update is complete. e500mc
601 * cores also require an isync.
603 lwz r0, 0xc08(r9) /* LAWAR0 */
607 * Read the current CCSRBARH and CCSRBARL using load word instructions.
608 * Follow this with an isync instruction. This forces any outstanding
609 * accesses to configuration space to completion.
612 lwz r0, 0(r9) /* CCSRBARH */
613 lwz r0, 4(r9) /* CCSRBARL */
617 * Write the new values for CCSRBARH and CCSRBARL to their old
618 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
619 * has a new value written it loads a CCSRBARH shadow register. When
620 * the CCSRBARL is written, the CCSRBARH shadow register contents
621 * along with the CCSRBARL value are loaded into the CCSRBARH and
622 * CCSRBARL registers, respectively. Follow this with a sync
626 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
627 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
628 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
629 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
631 ori r2, r2, CCSRAR_C@l
633 stw r0, 0(r9) /* Write to CCSRBARH */
634 sync /* Make sure we write to CCSRBARH first */
635 stw r1, 4(r9) /* Write to CCSRBARL */
639 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
640 * Follow this with a sync instruction.
645 /* Delete the temporary LAW */
654 #else /* #ifdef CONFIG_FSL_CORENET */
658 * Read the current value of CCSRBAR using a load word instruction
659 * followed by an isync. This forces all accesses to configuration
666 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
667 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
668 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
670 /* Write the new value to CCSRBAR. */
671 lis r0, CCSRBAR_PHYS_RS12@h
672 ori r0, r0, CCSRBAR_PHYS_RS12@l
677 * The manual says to perform a load of an address that does not
678 * access configuration space or the on-chip SRAM using an existing TLB,
679 * but that doesn't appear to be necessary. We will do the isync,
685 * Read the contents of CCSRBAR from its new location, followed by
691 #endif /* #ifdef CONFIG_FSL_CORENET */
693 /* Delete the temporary TLBs */
695 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
696 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
698 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
700 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
703 * Create a TLB for the MMR location of CCSR
704 * to access L2CSR0 register
706 create_tlb0_entry 0, \
707 0, BOOKE_PAGESZ_4K, \
708 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
709 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
710 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
712 enable_l2_cluster_l2:
713 /* enable L2 cache */
714 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
715 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
716 li r4, 33 /* stash id */
718 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
719 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
721 stw r4, 0(r3) /* invalidate L2 */
728 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
729 ori r4, r4, (L2CSR0_L2REP_MODE)@l
731 stw r4, 0(r3) /* enable L2 */
733 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
737 * Enable the L1. On e6500, this has to be done
738 * after the L2 is up.
741 #ifdef CONFIG_SYS_CACHE_STASHING
742 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
747 /* Enable/invalidate the I-Cache */
748 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
749 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
756 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
757 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
762 andi. r1,r3,L1CSR1_ICE@l
765 /* Enable/invalidate the D-Cache */
766 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
767 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
774 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
775 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
780 andi. r1,r3,L1CSR0_DCE@l
782 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
783 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
784 #define LAW_SIZE_1M 0x13
785 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
791 * Create a TLB entry for CCSR
793 * We're executing out of TLB1 entry in r14, and that's the only
794 * TLB entry that exists. To allocate some TLB entries for our
795 * own use, flip a bit high enough that we won't flip it again
800 lis r0, MAS0_TLBSEL(1)@h
801 rlwimi r0, r8, 16, MAS0_ESEL_MSK
802 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
803 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
804 lis r7, CONFIG_SYS_CCSRBAR@h
805 ori r7, r7, CONFIG_SYS_CCSRBAR@l
806 ori r2, r7, MAS2_I|MAS2_G
807 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
808 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
809 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
810 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
821 /* Map DCSR temporarily to physical address zero */
823 lis r3, DCSRBAR_LAWAR@h
824 ori r3, r3, DCSRBAR_LAWAR@l
826 stw r0, 0xc00(r7) /* LAWBARH0 */
827 stw r0, 0xc04(r7) /* LAWBARL0 */
829 stw r3, 0xc08(r7) /* LAWAR0 */
831 /* Read back from LAWAR to ensure the update is complete. */
832 lwz r3, 0xc08(r7) /* LAWAR0 */
835 /* Create a TLB entry for DCSR at zero */
838 lis r0, MAS0_TLBSEL(1)@h
839 rlwimi r0, r9, 16, MAS0_ESEL_MSK
840 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
841 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
842 li r6, 0 /* DCSR effective address */
843 ori r2, r6, MAS2_I|MAS2_G
844 li r3, MAS3_SW|MAS3_SR
856 /* enable the timebase */
857 #define CTBENR 0xe2084
859 addis r4, r7, CTBENR@ha
865 .macro erratum_set_ccsr offset value
866 addis r3, r7, \offset@ha
868 addi r3, r3, \offset@l
873 .macro erratum_set_dcsr offset value
874 addis r3, r6, \offset@ha
876 addi r3, r3, \offset@l
881 erratum_set_dcsr 0xb0e08 0xe0201800
882 erratum_set_dcsr 0xb0e18 0xe0201800
883 erratum_set_dcsr 0xb0e38 0xe0400000
884 erratum_set_dcsr 0xb0008 0x00900000
885 erratum_set_dcsr 0xb0e40 0xe00a0000
886 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
887 #ifdef CONFIG_RAMBOOT_PBL
888 erratum_set_ccsr 0x10f00 0x495e5000
890 erratum_set_ccsr 0x10f00 0x415e5000
892 erratum_set_ccsr 0x11f00 0x415e5000
894 /* Make temp mapping uncacheable again, if it was initially */
899 rlwimi r4, r15, 0, MAS2_I
900 rlwimi r4, r15, 0, MAS2_G
907 /* Clear the cache */
908 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
909 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
919 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
920 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
930 /* Remove temporary mappings */
931 lis r0, MAS0_TLBSEL(1)@h
932 rlwimi r0, r9, 16, MAS0_ESEL_MSK
942 stw r3, 0xc08(r7) /* LAWAR0 */
946 lis r0, MAS0_TLBSEL(1)@h
947 rlwimi r0, r8, 16, MAS0_ESEL_MSK
958 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
960 /* Lock two cache lines into I-Cache */
962 mfspr r11, SPRN_L1CSR1
963 rlwinm r11, r11, 0, ~L1CSR1_ICUL
966 mtspr SPRN_L1CSR1, r11
977 mfspr r11, SPRN_L1CSR1
978 3: andi. r11, r11, L1CSR1_ICUL
985 mfspr r11, SPRN_L1CSR1
986 3: andi. r11, r11, L1CSR1_ICUL
991 /* Inside a locked cacheline, wait a while, write, then wait a while */
995 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
996 4: mfspr r5, SPRN_TBRL
1003 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1004 4: mfspr r5, SPRN_TBRL
1011 * Fill out the rest of this cache line and the next with nops,
1012 * to ensure that nothing outside the locked area will be
1013 * fetched due to a branch.
1020 mfspr r11, SPRN_L1CSR1
1021 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1024 mtspr SPRN_L1CSR1, r11
1033 create_init_ram_area:
1034 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1035 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1038 /* create a temp mapping in AS=1 to the 4M boot window */
1039 create_tlb1_entry 15, \
1040 1, BOOKE_PAGESZ_4M, \
1041 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1042 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1045 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1046 /* create a temp mapping in AS = 1 for Flash mapping
1047 * created by PBL for ISBC code
1049 create_tlb1_entry 15, \
1050 1, BOOKE_PAGESZ_1M, \
1051 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1052 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1056 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1057 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1059 create_tlb1_entry 15, \
1060 1, BOOKE_PAGESZ_1M, \
1061 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1062 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1066 /* create a temp mapping in AS=1 to the stack */
1067 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1068 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1069 create_tlb1_entry 14, \
1070 1, BOOKE_PAGESZ_16K, \
1071 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1072 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1073 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1076 create_tlb1_entry 14, \
1077 1, BOOKE_PAGESZ_16K, \
1078 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1079 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1083 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1084 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1086 ori r7,r7,switch_as@l
1093 /* L1 DCache is used for initial RAM */
1095 /* Allocate Initial RAM in data cache.
1097 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1098 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1101 /* cache size * 1024 / (2 * L1 line size) */
1102 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1108 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1111 /* Jump out the last 4K page and continue to 'normal' start */
1112 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1113 /* We assume that we're already running at the address we're linked at */
1116 /* Calculate absolute address in FLASH and jump there */
1117 /*--------------------------------------------------------------*/
1118 lis r3,CONFIG_SYS_MONITOR_BASE@h
1119 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1120 addi r3,r3,_start_cont - _start + _START_OFFSET
1128 .long 0x27051956 /* U-BOOT Magic Number */
1129 .globl version_string
1131 .ascii U_BOOT_VERSION_STRING, "\0"
1136 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1137 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1138 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1140 stw r0,0(r3) /* Terminate Back Chain */
1141 stw r0,+4(r3) /* NULL return address. */
1142 mr r1,r3 /* Transfer to SP(r1) */
1147 /* switch back to AS = 0 */
1148 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1149 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1157 /* NOTREACHED - board_init_f() does not return */
1160 . = EXC_OFF_SYS_RESET
1161 .globl _start_of_vectors
1164 /* Critical input. */
1165 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1168 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1170 /* Data Storage exception. */
1171 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1173 /* Instruction Storage exception. */
1174 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1176 /* External Interrupt exception. */
1177 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1179 /* Alignment exception. */
1182 EXCEPTION_PROLOG(SRR0, SRR1)
1187 addi r3,r1,STACK_FRAME_OVERHEAD
1188 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1190 /* Program check exception */
1193 EXCEPTION_PROLOG(SRR0, SRR1)
1194 addi r3,r1,STACK_FRAME_OVERHEAD
1195 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1196 MSR_KERNEL, COPY_EE)
1198 /* No FPU on MPC85xx. This exception is not supposed to happen.
1200 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1204 * r0 - SYSCALL number
1208 addis r11,r0,0 /* get functions table addr */
1209 ori r11,r11,0 /* Note: this code is patched in trap_init */
1210 addis r12,r0,0 /* get number of functions */
1216 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1220 li r20,0xd00-4 /* Get stack pointer */
1222 subi r12,r12,12 /* Adjust stack pointer */
1223 li r0,0xc00+_end_back-SystemCall
1224 cmplw 0,r0,r12 /* Check stack overflow */
1235 li r12,0xc00+_back-SystemCall
1243 mfmsr r11 /* Disable interrupts */
1247 SYNC /* Some chip revs need this... */
1251 li r12,0xd00-4 /* restore regs */
1261 addi r12,r12,12 /* Adjust stack pointer */
1269 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1270 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1271 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1273 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1274 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1276 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1278 .globl _end_of_vectors
1282 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1285 * This code finishes saving the registers to the exception frame
1286 * and jumps to the appropriate handler for the exception.
1287 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1289 .globl transfer_to_handler
1290 transfer_to_handler:
1301 andi. r24,r23,0x3f00 /* get vector offset */
1305 mtspr SPRG2,r22 /* r1 is now kernel sp */
1307 lwz r24,0(r23) /* virtual address of handler */
1308 lwz r23,4(r23) /* where to go when done */
1313 rfi /* jump to handler, enable MMU */
1316 mfmsr r28 /* Disable interrupts */
1320 SYNC /* Some chip revs need this... */
1335 lwz r2,_NIP(r1) /* Restore environment */
1346 mfmsr r28 /* Disable interrupts */
1350 SYNC /* Some chip revs need this... */
1365 lwz r2,_NIP(r1) /* Restore environment */
1376 mfmsr r28 /* Disable interrupts */
1380 SYNC /* Some chip revs need this... */
1395 lwz r2,_NIP(r1) /* Restore environment */
1397 mtspr SPRN_MCSRR0,r2
1398 mtspr SPRN_MCSRR1,r0
1409 .globl invalidate_icache
1412 ori r0,r0,L1CSR1_ICFI
1417 blr /* entire I cache */
1419 .globl invalidate_dcache
1422 ori r0,r0,L1CSR0_DCFI
1429 .globl icache_enable
1432 bl invalidate_icache
1442 .globl icache_disable
1446 ori r3,r3,L1CSR1_ICE
1452 .globl icache_status
1455 andi. r3,r3,L1CSR1_ICE
1458 .globl dcache_enable
1461 bl invalidate_dcache
1473 .globl dcache_disable
1477 ori r4,r4,L1CSR0_DCE
1483 .globl dcache_status
1486 andi. r3,r3,L1CSR0_DCE
1509 /*------------------------------------------------------------------------------- */
1511 /* Description: Input 8 bits */
1512 /*------------------------------------------------------------------------------- */
1518 /*------------------------------------------------------------------------------- */
1519 /* Function: out8 */
1520 /* Description: Output 8 bits */
1521 /*------------------------------------------------------------------------------- */
1528 /*------------------------------------------------------------------------------- */
1529 /* Function: out16 */
1530 /* Description: Output 16 bits */
1531 /*------------------------------------------------------------------------------- */
1538 /*------------------------------------------------------------------------------- */
1539 /* Function: out16r */
1540 /* Description: Byte reverse and output 16 bits */
1541 /*------------------------------------------------------------------------------- */
1548 /*------------------------------------------------------------------------------- */
1549 /* Function: out32 */
1550 /* Description: Output 32 bits */
1551 /*------------------------------------------------------------------------------- */
1558 /*------------------------------------------------------------------------------- */
1559 /* Function: out32r */
1560 /* Description: Byte reverse and output 32 bits */
1561 /*------------------------------------------------------------------------------- */
1568 /*------------------------------------------------------------------------------- */
1569 /* Function: in16 */
1570 /* Description: Input 16 bits */
1571 /*------------------------------------------------------------------------------- */
1577 /*------------------------------------------------------------------------------- */
1578 /* Function: in16r */
1579 /* Description: Input 16 bits and byte reverse */
1580 /*------------------------------------------------------------------------------- */
1586 /*------------------------------------------------------------------------------- */
1587 /* Function: in32 */
1588 /* Description: Input 32 bits */
1589 /*------------------------------------------------------------------------------- */
1595 /*------------------------------------------------------------------------------- */
1596 /* Function: in32r */
1597 /* Description: Input 32 bits and byte reverse */
1598 /*------------------------------------------------------------------------------- */
1603 #endif /* !MINIMAL_SPL */
1605 /*------------------------------------------------------------------------------*/
1608 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1616 #ifdef CONFIG_ENABLE_36BIT_PHYS
1620 #ifdef CONFIG_SYS_BOOK3E_HV
1630 * void relocate_code (addr_sp, gd, addr_moni)
1632 * This "function" does not return, instead it continues in RAM
1633 * after relocating the monitor code.
1637 * r5 = length in bytes
1638 * r6 = cachelinesize
1640 .globl relocate_code
1642 mr r1,r3 /* Set new stack pointer */
1643 mr r9,r4 /* Save copy of Init Data pointer */
1644 mr r10,r5 /* Save copy of Destination Address */
1647 mr r3,r5 /* Destination Address */
1648 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1649 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1650 lwz r5,GOT(__init_end)
1652 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1657 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1663 /* First our own GOT */
1665 /* the the one used by the C code */
1675 beq cr1,4f /* In place copy is not necessary */
1676 beq 7f /* Protect against 0 count */
1695 * Now flush the cache: note that we must start from a cache aligned
1696 * address. Otherwise we might miss one cache line.
1700 beq 7f /* Always flush prefetch queue in any case */
1708 sync /* Wait for all dcbst to complete on bus */
1714 7: sync /* Wait for all icbi to complete on bus */
1718 * We are done. Do not return, instead branch to second part of board
1719 * initialization, now running from RAM.
1722 addi r0,r10,in_ram - _start + _START_OFFSET
1725 * As IVPR is going to point RAM address,
1726 * Make sure IVOR15 has valid opcode to support debugger
1731 * Re-point the IVPR at RAM
1736 blr /* NEVER RETURNS! */
1741 * Relocation Function, r12 point to got2+0x8000
1743 * Adjust got2 pointers, no need to check for 0, this code
1744 * already puts a few entries in the table.
1746 li r0,__got2_entries@sectoff@l
1747 la r3,GOT(_GOT2_TABLE_)
1748 lwz r11,GOT(_GOT2_TABLE_)
1760 * Now adjust the fixups and the pointers to the fixups
1761 * in case we need to move ourselves again.
1763 li r0,__fixup_entries@sectoff@l
1764 lwz r3,GOT(_FIXUP_TABLE_)
1780 * Now clear BSS segment
1782 lwz r3,GOT(__bss_start)
1783 lwz r4,GOT(__bss_end)
1796 mr r3,r9 /* Init Data pointer */
1797 mr r4,r10 /* Destination Address */
1802 * Copy exception vector code to low memory
1805 * r7: source address, r8: end address, r9: target address
1809 mflr r4 /* save link register */
1811 lwz r7,GOT(_start_of_vectors)
1812 lwz r8,GOT(_end_of_vectors)
1814 li r9,0x100 /* reset vector always at 0x100 */
1817 bgelr /* return if r7>=r8 - just in case */
1827 * relocate `hdlr' and `int_return' entries
1829 li r7,.L_CriticalInput - _start + _START_OFFSET
1831 li r7,.L_MachineCheck - _start + _START_OFFSET
1833 li r7,.L_DataStorage - _start + _START_OFFSET
1835 li r7,.L_InstStorage - _start + _START_OFFSET
1837 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1839 li r7,.L_Alignment - _start + _START_OFFSET
1841 li r7,.L_ProgramCheck - _start + _START_OFFSET
1843 li r7,.L_FPUnavailable - _start + _START_OFFSET
1845 li r7,.L_Decrementer - _start + _START_OFFSET
1847 li r7,.L_IntervalTimer - _start + _START_OFFSET
1848 li r8,_end_of_vectors - _start + _START_OFFSET
1851 addi r7,r7,0x100 /* next exception vector */
1855 /* Update IVORs as per relocated vector table address */
1857 mtspr IVOR0,r7 /* 0: Critical input */
1859 mtspr IVOR1,r7 /* 1: Machine check */
1861 mtspr IVOR2,r7 /* 2: Data storage */
1863 mtspr IVOR3,r7 /* 3: Instruction storage */
1865 mtspr IVOR4,r7 /* 4: External interrupt */
1867 mtspr IVOR5,r7 /* 5: Alignment */
1869 mtspr IVOR6,r7 /* 6: Program check */
1871 mtspr IVOR7,r7 /* 7: floating point unavailable */
1873 mtspr IVOR8,r7 /* 8: System call */
1874 /* 9: Auxiliary processor unavailable(unsupported) */
1876 mtspr IVOR10,r7 /* 10: Decrementer */
1878 mtspr IVOR11,r7 /* 11: Interval timer */
1880 mtspr IVOR12,r7 /* 12: Watchdog timer */
1882 mtspr IVOR13,r7 /* 13: Data TLB error */
1884 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1886 mtspr IVOR15,r7 /* 15: Debug */
1891 mtlr r4 /* restore link register */
1894 .globl unlock_ram_in_cache
1895 unlock_ram_in_cache:
1896 /* invalidate the INIT_RAM section */
1897 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1898 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1901 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1905 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1909 /* Invalidate the TLB entries for the cache */
1910 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1911 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1924 mfspr r3,SPRN_L1CFG0
1926 rlwinm r5,r3,9,3 /* Extract cache block size */
1927 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1928 * are currently defined.
1931 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1932 * log2(number of ways)
1934 slw r5,r4,r5 /* r5 = cache block size */
1936 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1937 mulli r7,r7,13 /* An 8-way cache will require 13
1942 /* save off HID0 and set DCFA */
1944 ori r9,r8,HID0_DCFA@l
1951 1: lwz r3,0(r4) /* Load... */
1959 1: dcbf 0,r4 /* ...and flush. */
1972 #include "fixed_ivor.S"
1974 #endif /* !MINIMAL_SPL */