2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
10 * The processor starts at 0xfffffffc and the code is first executed in the
11 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
15 #include <asm-offsets.h>
20 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
22 #include <ppc_asm.tmpl>
25 #include <asm/cache.h>
29 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
31 #if defined(CONFIG_NAND_SPL) || \
32 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
36 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
37 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
42 * Set up GOT: Global Offset Table
44 * Use r12 to access the GOT
47 GOT_ENTRY(_GOT2_TABLE_)
48 GOT_ENTRY(_FIXUP_TABLE_)
52 GOT_ENTRY(_start_of_vectors)
53 GOT_ENTRY(_end_of_vectors)
54 GOT_ENTRY(transfer_to_handler)
59 GOT_ENTRY(__bss_start)
63 * e500 Startup -- after reset only the last 4KB of the effective
64 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
65 * section is located at THIS LAST page and basically does three
66 * things: clear some registers, set up exception tables and
67 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
68 * continue the boot procedure.
70 * Once the boot rom is mapped by TLB entries we can proceed
71 * with normal startup.
79 /* Enable debug exception */
83 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
86 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
90 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
91 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
96 /* Not a supported revision affected by erratum */
100 1: li r27,1 /* Remember for later that we have the erratum */
101 /* Erratum says set bits 55:60 to 001001 */
111 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
114 mfspr r3, SPRN_HDBCR0
116 mtspr SPRN_HDBCR0, r3
120 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
121 /* ISBC uses L2 as stack.
122 * Disable L2 cache here so that u-boot can enable it later
123 * as part of it's normal flow
126 /* Check if L2 is enabled */
127 mfspr r3, SPRN_L2CSR0
129 ori r2, r2, L2CSR0_L2E@l
133 mfspr r3, SPRN_L2CSR0
135 lis r2,(L2CSR0_L2FL)@h
136 ori r2, r2, (L2CSR0_L2FL)@l
143 mfspr r3, SPRN_L2CSR0
147 mfspr r3, SPRN_L2CSR0
149 ori r2, r2, L2CSR0_L2E@l
159 /* clear registers/arrays not reset by hardware */
163 mtspr L1CSR0,r0 /* invalidate d-cache */
164 mtspr L1CSR1,r0 /* invalidate i-cache */
167 mtspr DBSR,r1 /* Clear all valid bits */
170 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
171 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
172 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
174 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
175 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
177 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
178 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
180 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
181 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
183 lis \scratch, \phy_high@h
184 ori \scratch, \scratch, \phy_high@l
192 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
193 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
194 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
196 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
197 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
199 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
200 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
202 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
203 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
205 lis \scratch, \phy_high@h
206 ori \scratch, \scratch, \phy_high@l
214 .macro delete_tlb1_entry esel scratch
215 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
216 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
226 .macro delete_tlb0_entry esel epn wimg scratch
227 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
228 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
232 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
233 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
241 /* Interrupt vectors do not fit in minimal SPL. */
242 #if !defined(MINIMAL_SPL)
243 /* Setup interrupt vectors */
244 lis r1,CONFIG_SYS_MONITOR_BASE@h
247 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
248 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
250 addi r4,r3,CriticalInput - _start + _START_OFFSET
251 mtspr IVOR0,r4 /* 0: Critical input */
252 addi r4,r3,MachineCheck - _start + _START_OFFSET
253 mtspr IVOR1,r4 /* 1: Machine check */
254 addi r4,r3,DataStorage - _start + _START_OFFSET
255 mtspr IVOR2,r4 /* 2: Data storage */
256 addi r4,r3,InstStorage - _start + _START_OFFSET
257 mtspr IVOR3,r4 /* 3: Instruction storage */
258 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
259 mtspr IVOR4,r4 /* 4: External interrupt */
260 addi r4,r3,Alignment - _start + _START_OFFSET
261 mtspr IVOR5,r4 /* 5: Alignment */
262 addi r4,r3,ProgramCheck - _start + _START_OFFSET
263 mtspr IVOR6,r4 /* 6: Program check */
264 addi r4,r3,FPUnavailable - _start + _START_OFFSET
265 mtspr IVOR7,r4 /* 7: floating point unavailable */
266 addi r4,r3,SystemCall - _start + _START_OFFSET
267 mtspr IVOR8,r4 /* 8: System call */
268 /* 9: Auxiliary processor unavailable(unsupported) */
269 addi r4,r3,Decrementer - _start + _START_OFFSET
270 mtspr IVOR10,r4 /* 10: Decrementer */
271 addi r4,r3,IntervalTimer - _start + _START_OFFSET
272 mtspr IVOR11,r4 /* 11: Interval timer */
273 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
274 mtspr IVOR12,r4 /* 12: Watchdog timer */
275 addi r4,r3,DataTLBError - _start + _START_OFFSET
276 mtspr IVOR13,r4 /* 13: Data TLB error */
277 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
278 mtspr IVOR14,r4 /* 14: Instruction TLB error */
279 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
280 mtspr IVOR15,r4 /* 15: Debug */
283 /* Clear and set up some registers. */
286 mtspr DEC,r0 /* prevent dec exceptions */
287 mttbl r0 /* prevent fit & wdt exceptions */
289 mtspr TSR,r1 /* clear all timer exception status */
290 mtspr TCR,r0 /* disable all */
291 mtspr ESR,r0 /* clear exception syndrome register */
292 mtspr MCSR,r0 /* machine check syndrome register */
293 mtxer r0 /* clear integer exception register */
295 #ifdef CONFIG_SYS_BOOK3E_HV
296 mtspr MAS8,r0 /* make sure MAS8 is clear */
299 /* Enable Time Base and Select Time Base Clock */
300 lis r0,HID0_EMCP@h /* Enable machine check */
301 #if defined(CONFIG_ENABLE_36BIT_PHYS)
302 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
304 #ifndef CONFIG_E500MC
305 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
309 #ifndef CONFIG_E500MC
310 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
313 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
315 /* Set MBDD bit also */
316 ori r0, r0, HID1_MBDD@l
321 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
327 /* Enable Branch Prediction */
328 #if defined(CONFIG_BTB)
329 lis r0,BUCSR_ENABLE@h
330 ori r0,r0,BUCSR_ENABLE@l
334 #if defined(CONFIG_SYS_INIT_DBCR)
337 mtspr DBSR,r1 /* Clear all status bits */
338 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
339 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
343 #ifdef CONFIG_MPC8569
344 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
345 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
347 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
348 * use address space which is more than 12bits, and it must be done in
349 * the 4K boot page. So we set this bit here.
352 /* create a temp mapping TLB0[0] for LBCR */
353 create_tlb0_entry 0, \
354 0, BOOKE_PAGESZ_4K, \
355 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
356 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
359 /* Set LBCR register */
360 lis r4,CONFIG_SYS_LBCR_ADDR@h
361 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
363 lis r5,CONFIG_SYS_LBC_LBCR@h
364 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
368 /* invalidate this temp TLB */
369 lis r4,CONFIG_SYS_LBC_ADDR@h
370 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
374 #endif /* CONFIG_MPC8569 */
377 * Search for the TLB that covers the code we're executing, and shrink it
378 * so that it covers only this 4K page. That will ensure that any other
379 * TLB we create won't interfere with it. We assume that the TLB exists,
380 * which is why we don't check the Valid bit of MAS1. We also assume
383 * This is necessary, for example, when booting from the on-chip ROM,
384 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
386 bl nexti /* Find our address */
387 nexti: mflr r1 /* R1 = our PC */
389 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
392 tlbsx 0, r1 /* This must succeed */
394 mfspr r14, MAS0 /* Save ESEL for later */
395 rlwinm r14, r14, 16, 0xfff
397 /* Set the size of the TLB to 4KB */
400 andc r3, r3, r2 /* Clear the TSIZE bits */
401 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
402 oris r3, r3, MAS1_IPROT@h
406 * Set the base address of the TLB to our PC. We assume that
407 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
410 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
412 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
417 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
420 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
421 rlwinm r2, r2, 0, ~MAS2_I
425 mtspr MAS2, r2 /* Set the EPN to our PC base address */
430 mtspr MAS3, r2 /* Set the RPN to our PC base address */
437 * Clear out any other TLB entries that may exist, to avoid conflicts.
438 * Our TLB entry is in r14.
440 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
444 mfspr r4, SPRN_TLB1CFG
445 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
450 rlwinm r5, r3, 16, MAS0_ESEL_MSK
452 beq 2f /* skip the entry we're executing from */
454 oris r5, r5, MAS0_TLBSEL(1)@h
465 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
467 * TLB entry for debuggging in AS1
468 * Create temporary TLB entry in AS0 to handle debug exception
469 * As on debug exception MSR is cleared i.e. Address space is changed
470 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
476 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
477 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
478 * and this window is outside of 4K boot window.
480 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
481 0, BOOKE_PAGESZ_4M, \
482 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
483 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
486 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
487 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
488 0, BOOKE_PAGESZ_1M, \
489 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
490 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
494 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
495 * because "nexti" will resize TLB to 4K
497 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
498 0, BOOKE_PAGESZ_256K, \
499 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
500 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
506 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
507 * location is not where we want it. This typically happens on a 36-bit
508 * system, where we want to move CCSR to near the top of 36-bit address space.
510 * To move CCSR, we create two temporary TLBs, one for the old location, and
511 * another for the new location. On CoreNet systems, we also need to create
512 * a special, temporary LAW.
514 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
515 * long-term TLBs, so we use TLB0 here.
517 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
519 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
520 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
525 * Create a TLB for the new location of CCSR. Register R8 is reserved
526 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
528 lis r8, CONFIG_SYS_CCSRBAR@h
529 ori r8, r8, CONFIG_SYS_CCSRBAR@l
530 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
531 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
532 create_tlb0_entry 0, \
533 0, BOOKE_PAGESZ_4K, \
534 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
535 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
536 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
538 * Create a TLB for the current location of CCSR. Register R9 is reserved
539 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
542 create_tlb0_entry 1, \
543 0, BOOKE_PAGESZ_4K, \
544 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
545 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
546 0, r3 /* The default CCSR address is always a 32-bit number */
550 * We have a TLB for what we think is the current (old) CCSR. Let's
551 * verify that, otherwise we won't be able to move it.
552 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
553 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
556 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
557 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
558 #ifdef CONFIG_FSL_CORENET
559 lwz r1, 4(r9) /* CCSRBARL */
561 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
568 * If the value we read from CCSRBARL is not what we expect, then
569 * enter an infinite loop. This will at least allow a debugger to
570 * halt execution and examine TLBs, etc. There's no point in going
574 bne infinite_debug_loop
576 #ifdef CONFIG_FSL_CORENET
578 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
579 #define LAW_EN 0x80000000
580 #define LAW_SIZE_4K 0xb
581 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
582 #define CCSRAR_C 0x80000000 /* Commit */
586 * On CoreNet systems, we create the temporary LAW using a special LAW
587 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
589 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
590 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
591 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
592 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
593 lis r2, CCSRBAR_LAWAR@h
594 ori r2, r2, CCSRBAR_LAWAR@l
596 stw r0, 0xc00(r9) /* LAWBARH0 */
597 stw r1, 0xc04(r9) /* LAWBARL0 */
599 stw r2, 0xc08(r9) /* LAWAR0 */
602 * Read back from LAWAR to ensure the update is complete. e500mc
603 * cores also require an isync.
605 lwz r0, 0xc08(r9) /* LAWAR0 */
609 * Read the current CCSRBARH and CCSRBARL using load word instructions.
610 * Follow this with an isync instruction. This forces any outstanding
611 * accesses to configuration space to completion.
614 lwz r0, 0(r9) /* CCSRBARH */
615 lwz r0, 4(r9) /* CCSRBARL */
619 * Write the new values for CCSRBARH and CCSRBARL to their old
620 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
621 * has a new value written it loads a CCSRBARH shadow register. When
622 * the CCSRBARL is written, the CCSRBARH shadow register contents
623 * along with the CCSRBARL value are loaded into the CCSRBARH and
624 * CCSRBARL registers, respectively. Follow this with a sync
628 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
629 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
630 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
631 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
633 ori r2, r2, CCSRAR_C@l
635 stw r0, 0(r9) /* Write to CCSRBARH */
636 sync /* Make sure we write to CCSRBARH first */
637 stw r1, 4(r9) /* Write to CCSRBARL */
641 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
642 * Follow this with a sync instruction.
647 /* Delete the temporary LAW */
656 #else /* #ifdef CONFIG_FSL_CORENET */
660 * Read the current value of CCSRBAR using a load word instruction
661 * followed by an isync. This forces all accesses to configuration
668 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
669 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
670 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
672 /* Write the new value to CCSRBAR. */
673 lis r0, CCSRBAR_PHYS_RS12@h
674 ori r0, r0, CCSRBAR_PHYS_RS12@l
679 * The manual says to perform a load of an address that does not
680 * access configuration space or the on-chip SRAM using an existing TLB,
681 * but that doesn't appear to be necessary. We will do the isync,
687 * Read the contents of CCSRBAR from its new location, followed by
693 #endif /* #ifdef CONFIG_FSL_CORENET */
695 /* Delete the temporary TLBs */
697 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
698 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
700 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
702 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
705 * Create a TLB for the MMR location of CCSR
706 * to access L2CSR0 register
708 create_tlb0_entry 0, \
709 0, BOOKE_PAGESZ_4K, \
710 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
711 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
712 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
714 enable_l2_cluster_l2:
715 /* enable L2 cache */
716 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
717 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
718 li r4, 33 /* stash id */
720 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
721 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
723 stw r4, 0(r3) /* invalidate L2 */
730 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
731 ori r4, r4, (L2CSR0_L2REP_MODE)@l
733 stw r4, 0(r3) /* enable L2 */
735 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
739 * Enable the L1. On e6500, this has to be done
740 * after the L2 is up.
743 #ifdef CONFIG_SYS_CACHE_STASHING
744 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
749 /* Enable/invalidate the I-Cache */
750 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
751 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
758 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
759 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
764 andi. r1,r3,L1CSR1_ICE@l
767 /* Enable/invalidate the D-Cache */
768 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
769 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
776 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
777 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
782 andi. r1,r3,L1CSR0_DCE@l
784 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
785 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
786 #define LAW_SIZE_1M 0x13
787 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
793 * Create a TLB entry for CCSR
795 * We're executing out of TLB1 entry in r14, and that's the only
796 * TLB entry that exists. To allocate some TLB entries for our
797 * own use, flip a bit high enough that we won't flip it again
802 lis r0, MAS0_TLBSEL(1)@h
803 rlwimi r0, r8, 16, MAS0_ESEL_MSK
804 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
805 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
806 lis r7, CONFIG_SYS_CCSRBAR@h
807 ori r7, r7, CONFIG_SYS_CCSRBAR@l
808 ori r2, r7, MAS2_I|MAS2_G
809 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
810 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
811 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
812 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
823 /* Map DCSR temporarily to physical address zero */
825 lis r3, DCSRBAR_LAWAR@h
826 ori r3, r3, DCSRBAR_LAWAR@l
828 stw r0, 0xc00(r7) /* LAWBARH0 */
829 stw r0, 0xc04(r7) /* LAWBARL0 */
831 stw r3, 0xc08(r7) /* LAWAR0 */
833 /* Read back from LAWAR to ensure the update is complete. */
834 lwz r3, 0xc08(r7) /* LAWAR0 */
837 /* Create a TLB entry for DCSR at zero */
840 lis r0, MAS0_TLBSEL(1)@h
841 rlwimi r0, r9, 16, MAS0_ESEL_MSK
842 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
843 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
844 li r6, 0 /* DCSR effective address */
845 ori r2, r6, MAS2_I|MAS2_G
846 li r3, MAS3_SW|MAS3_SR
858 /* enable the timebase */
859 #define CTBENR 0xe2084
861 addis r4, r7, CTBENR@ha
867 .macro erratum_set_ccsr offset value
868 addis r3, r7, \offset@ha
870 addi r3, r3, \offset@l
875 .macro erratum_set_dcsr offset value
876 addis r3, r6, \offset@ha
878 addi r3, r3, \offset@l
883 erratum_set_dcsr 0xb0e08 0xe0201800
884 erratum_set_dcsr 0xb0e18 0xe0201800
885 erratum_set_dcsr 0xb0e38 0xe0400000
886 erratum_set_dcsr 0xb0008 0x00900000
887 erratum_set_dcsr 0xb0e40 0xe00a0000
888 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
889 #ifdef CONFIG_RAMBOOT_PBL
890 erratum_set_ccsr 0x10f00 0x495e5000
892 erratum_set_ccsr 0x10f00 0x415e5000
894 erratum_set_ccsr 0x11f00 0x415e5000
896 /* Make temp mapping uncacheable again, if it was initially */
901 rlwimi r4, r15, 0, MAS2_I
902 rlwimi r4, r15, 0, MAS2_G
909 /* Clear the cache */
910 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
911 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
921 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
922 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
932 /* Remove temporary mappings */
933 lis r0, MAS0_TLBSEL(1)@h
934 rlwimi r0, r9, 16, MAS0_ESEL_MSK
944 stw r3, 0xc08(r7) /* LAWAR0 */
948 lis r0, MAS0_TLBSEL(1)@h
949 rlwimi r0, r8, 16, MAS0_ESEL_MSK
960 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
962 /* Lock two cache lines into I-Cache */
964 mfspr r11, SPRN_L1CSR1
965 rlwinm r11, r11, 0, ~L1CSR1_ICUL
968 mtspr SPRN_L1CSR1, r11
979 mfspr r11, SPRN_L1CSR1
980 3: andi. r11, r11, L1CSR1_ICUL
987 mfspr r11, SPRN_L1CSR1
988 3: andi. r11, r11, L1CSR1_ICUL
993 /* Inside a locked cacheline, wait a while, write, then wait a while */
997 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
998 4: mfspr r5, SPRN_TBRL
1005 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1006 4: mfspr r5, SPRN_TBRL
1013 * Fill out the rest of this cache line and the next with nops,
1014 * to ensure that nothing outside the locked area will be
1015 * fetched due to a branch.
1022 mfspr r11, SPRN_L1CSR1
1023 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1026 mtspr SPRN_L1CSR1, r11
1035 create_init_ram_area:
1036 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1037 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1040 /* create a temp mapping in AS=1 to the 4M boot window */
1041 create_tlb1_entry 15, \
1042 1, BOOKE_PAGESZ_4M, \
1043 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1044 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1047 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1048 /* create a temp mapping in AS = 1 for Flash mapping
1049 * created by PBL for ISBC code
1051 create_tlb1_entry 15, \
1052 1, BOOKE_PAGESZ_1M, \
1053 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1054 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1058 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1059 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1061 create_tlb1_entry 15, \
1062 1, BOOKE_PAGESZ_1M, \
1063 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1064 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1068 /* create a temp mapping in AS=1 to the stack */
1069 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1070 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1071 create_tlb1_entry 14, \
1072 1, BOOKE_PAGESZ_16K, \
1073 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1074 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1075 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1078 create_tlb1_entry 14, \
1079 1, BOOKE_PAGESZ_16K, \
1080 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1081 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1085 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1086 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1088 ori r7,r7,switch_as@l
1095 /* L1 DCache is used for initial RAM */
1097 /* Allocate Initial RAM in data cache.
1099 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1100 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1103 /* cache size * 1024 / (2 * L1 line size) */
1104 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1110 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1113 /* Jump out the last 4K page and continue to 'normal' start */
1114 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1115 /* We assume that we're already running at the address we're linked at */
1118 /* Calculate absolute address in FLASH and jump there */
1119 /*--------------------------------------------------------------*/
1120 lis r3,CONFIG_SYS_MONITOR_BASE@h
1121 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1122 addi r3,r3,_start_cont - _start + _START_OFFSET
1130 .long 0x27051956 /* U-BOOT Magic Number */
1131 .globl version_string
1133 .ascii U_BOOT_VERSION_STRING, "\0"
1138 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1139 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1140 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1142 stw r0,0(r3) /* Terminate Back Chain */
1143 stw r0,+4(r3) /* NULL return address. */
1144 mr r1,r3 /* Transfer to SP(r1) */
1149 /* switch back to AS = 0 */
1150 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1151 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1159 /* NOTREACHED - board_init_f() does not return */
1162 . = EXC_OFF_SYS_RESET
1163 .globl _start_of_vectors
1166 /* Critical input. */
1167 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1170 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1172 /* Data Storage exception. */
1173 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1175 /* Instruction Storage exception. */
1176 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1178 /* External Interrupt exception. */
1179 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1181 /* Alignment exception. */
1184 EXCEPTION_PROLOG(SRR0, SRR1)
1189 addi r3,r1,STACK_FRAME_OVERHEAD
1190 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1192 /* Program check exception */
1195 EXCEPTION_PROLOG(SRR0, SRR1)
1196 addi r3,r1,STACK_FRAME_OVERHEAD
1197 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1198 MSR_KERNEL, COPY_EE)
1200 /* No FPU on MPC85xx. This exception is not supposed to happen.
1202 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1206 * r0 - SYSCALL number
1210 addis r11,r0,0 /* get functions table addr */
1211 ori r11,r11,0 /* Note: this code is patched in trap_init */
1212 addis r12,r0,0 /* get number of functions */
1218 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1222 li r20,0xd00-4 /* Get stack pointer */
1224 subi r12,r12,12 /* Adjust stack pointer */
1225 li r0,0xc00+_end_back-SystemCall
1226 cmplw 0,r0,r12 /* Check stack overflow */
1237 li r12,0xc00+_back-SystemCall
1245 mfmsr r11 /* Disable interrupts */
1249 SYNC /* Some chip revs need this... */
1253 li r12,0xd00-4 /* restore regs */
1263 addi r12,r12,12 /* Adjust stack pointer */
1271 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1272 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1273 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1275 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1276 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1278 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1280 .globl _end_of_vectors
1284 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1287 * This code finishes saving the registers to the exception frame
1288 * and jumps to the appropriate handler for the exception.
1289 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1291 .globl transfer_to_handler
1292 transfer_to_handler:
1303 andi. r24,r23,0x3f00 /* get vector offset */
1307 mtspr SPRG2,r22 /* r1 is now kernel sp */
1309 lwz r24,0(r23) /* virtual address of handler */
1310 lwz r23,4(r23) /* where to go when done */
1315 rfi /* jump to handler, enable MMU */
1318 mfmsr r28 /* Disable interrupts */
1322 SYNC /* Some chip revs need this... */
1337 lwz r2,_NIP(r1) /* Restore environment */
1348 mfmsr r28 /* Disable interrupts */
1352 SYNC /* Some chip revs need this... */
1367 lwz r2,_NIP(r1) /* Restore environment */
1378 mfmsr r28 /* Disable interrupts */
1382 SYNC /* Some chip revs need this... */
1397 lwz r2,_NIP(r1) /* Restore environment */
1399 mtspr SPRN_MCSRR0,r2
1400 mtspr SPRN_MCSRR1,r0
1411 .globl invalidate_icache
1414 ori r0,r0,L1CSR1_ICFI
1419 blr /* entire I cache */
1421 .globl invalidate_dcache
1424 ori r0,r0,L1CSR0_DCFI
1431 .globl icache_enable
1434 bl invalidate_icache
1444 .globl icache_disable
1448 ori r3,r3,L1CSR1_ICE
1454 .globl icache_status
1457 andi. r3,r3,L1CSR1_ICE
1460 .globl dcache_enable
1463 bl invalidate_dcache
1475 .globl dcache_disable
1479 ori r4,r4,L1CSR0_DCE
1485 .globl dcache_status
1488 andi. r3,r3,L1CSR0_DCE
1511 /*------------------------------------------------------------------------------- */
1513 /* Description: Input 8 bits */
1514 /*------------------------------------------------------------------------------- */
1520 /*------------------------------------------------------------------------------- */
1521 /* Function: out8 */
1522 /* Description: Output 8 bits */
1523 /*------------------------------------------------------------------------------- */
1530 /*------------------------------------------------------------------------------- */
1531 /* Function: out16 */
1532 /* Description: Output 16 bits */
1533 /*------------------------------------------------------------------------------- */
1540 /*------------------------------------------------------------------------------- */
1541 /* Function: out16r */
1542 /* Description: Byte reverse and output 16 bits */
1543 /*------------------------------------------------------------------------------- */
1550 /*------------------------------------------------------------------------------- */
1551 /* Function: out32 */
1552 /* Description: Output 32 bits */
1553 /*------------------------------------------------------------------------------- */
1560 /*------------------------------------------------------------------------------- */
1561 /* Function: out32r */
1562 /* Description: Byte reverse and output 32 bits */
1563 /*------------------------------------------------------------------------------- */
1570 /*------------------------------------------------------------------------------- */
1571 /* Function: in16 */
1572 /* Description: Input 16 bits */
1573 /*------------------------------------------------------------------------------- */
1579 /*------------------------------------------------------------------------------- */
1580 /* Function: in16r */
1581 /* Description: Input 16 bits and byte reverse */
1582 /*------------------------------------------------------------------------------- */
1588 /*------------------------------------------------------------------------------- */
1589 /* Function: in32 */
1590 /* Description: Input 32 bits */
1591 /*------------------------------------------------------------------------------- */
1597 /*------------------------------------------------------------------------------- */
1598 /* Function: in32r */
1599 /* Description: Input 32 bits and byte reverse */
1600 /*------------------------------------------------------------------------------- */
1605 #endif /* !MINIMAL_SPL */
1607 /*------------------------------------------------------------------------------*/
1610 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1618 #ifdef CONFIG_ENABLE_36BIT_PHYS
1622 #ifdef CONFIG_SYS_BOOK3E_HV
1632 * void relocate_code (addr_sp, gd, addr_moni)
1634 * This "function" does not return, instead it continues in RAM
1635 * after relocating the monitor code.
1639 * r5 = length in bytes
1640 * r6 = cachelinesize
1642 .globl relocate_code
1644 mr r1,r3 /* Set new stack pointer */
1645 mr r9,r4 /* Save copy of Init Data pointer */
1646 mr r10,r5 /* Save copy of Destination Address */
1649 mr r3,r5 /* Destination Address */
1650 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1651 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1652 lwz r5,GOT(__init_end)
1654 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1659 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1665 /* First our own GOT */
1667 /* the the one used by the C code */
1677 beq cr1,4f /* In place copy is not necessary */
1678 beq 7f /* Protect against 0 count */
1697 * Now flush the cache: note that we must start from a cache aligned
1698 * address. Otherwise we might miss one cache line.
1702 beq 7f /* Always flush prefetch queue in any case */
1710 sync /* Wait for all dcbst to complete on bus */
1716 7: sync /* Wait for all icbi to complete on bus */
1720 * We are done. Do not return, instead branch to second part of board
1721 * initialization, now running from RAM.
1724 addi r0,r10,in_ram - _start + _START_OFFSET
1727 * As IVPR is going to point RAM address,
1728 * Make sure IVOR15 has valid opcode to support debugger
1733 * Re-point the IVPR at RAM
1738 blr /* NEVER RETURNS! */
1743 * Relocation Function, r12 point to got2+0x8000
1745 * Adjust got2 pointers, no need to check for 0, this code
1746 * already puts a few entries in the table.
1748 li r0,__got2_entries@sectoff@l
1749 la r3,GOT(_GOT2_TABLE_)
1750 lwz r11,GOT(_GOT2_TABLE_)
1762 * Now adjust the fixups and the pointers to the fixups
1763 * in case we need to move ourselves again.
1765 li r0,__fixup_entries@sectoff@l
1766 lwz r3,GOT(_FIXUP_TABLE_)
1782 * Now clear BSS segment
1784 lwz r3,GOT(__bss_start)
1785 lwz r4,GOT(__bss_end)
1798 mr r3,r9 /* Init Data pointer */
1799 mr r4,r10 /* Destination Address */
1804 * Copy exception vector code to low memory
1807 * r7: source address, r8: end address, r9: target address
1811 mflr r4 /* save link register */
1813 lwz r7,GOT(_start_of_vectors)
1814 lwz r8,GOT(_end_of_vectors)
1816 li r9,0x100 /* reset vector always at 0x100 */
1819 bgelr /* return if r7>=r8 - just in case */
1829 * relocate `hdlr' and `int_return' entries
1831 li r7,.L_CriticalInput - _start + _START_OFFSET
1833 li r7,.L_MachineCheck - _start + _START_OFFSET
1835 li r7,.L_DataStorage - _start + _START_OFFSET
1837 li r7,.L_InstStorage - _start + _START_OFFSET
1839 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1841 li r7,.L_Alignment - _start + _START_OFFSET
1843 li r7,.L_ProgramCheck - _start + _START_OFFSET
1845 li r7,.L_FPUnavailable - _start + _START_OFFSET
1847 li r7,.L_Decrementer - _start + _START_OFFSET
1849 li r7,.L_IntervalTimer - _start + _START_OFFSET
1850 li r8,_end_of_vectors - _start + _START_OFFSET
1853 addi r7,r7,0x100 /* next exception vector */
1857 /* Update IVORs as per relocated vector table address */
1859 mtspr IVOR0,r7 /* 0: Critical input */
1861 mtspr IVOR1,r7 /* 1: Machine check */
1863 mtspr IVOR2,r7 /* 2: Data storage */
1865 mtspr IVOR3,r7 /* 3: Instruction storage */
1867 mtspr IVOR4,r7 /* 4: External interrupt */
1869 mtspr IVOR5,r7 /* 5: Alignment */
1871 mtspr IVOR6,r7 /* 6: Program check */
1873 mtspr IVOR7,r7 /* 7: floating point unavailable */
1875 mtspr IVOR8,r7 /* 8: System call */
1876 /* 9: Auxiliary processor unavailable(unsupported) */
1878 mtspr IVOR10,r7 /* 10: Decrementer */
1880 mtspr IVOR11,r7 /* 11: Interval timer */
1882 mtspr IVOR12,r7 /* 12: Watchdog timer */
1884 mtspr IVOR13,r7 /* 13: Data TLB error */
1886 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1888 mtspr IVOR15,r7 /* 15: Debug */
1893 mtlr r4 /* restore link register */
1896 .globl unlock_ram_in_cache
1897 unlock_ram_in_cache:
1898 /* invalidate the INIT_RAM section */
1899 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1900 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1903 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1907 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1911 /* Invalidate the TLB entries for the cache */
1912 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1913 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1926 mfspr r3,SPRN_L1CFG0
1928 rlwinm r5,r3,9,3 /* Extract cache block size */
1929 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1930 * are currently defined.
1933 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1934 * log2(number of ways)
1936 slw r5,r4,r5 /* r5 = cache block size */
1938 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1939 mulli r7,r7,13 /* An 8-way cache will require 13
1944 /* save off HID0 and set DCFA */
1946 ori r9,r8,HID0_DCFA@l
1953 1: lwz r3,0(r4) /* Load... */
1961 1: dcbf 0,r4 /* ...and flush. */
1974 #include "fixed_ivor.S"
1976 #endif /* !MINIMAL_SPL */