1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
4 * Copyright (C) 2003 Motorola,Inc.
7 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
9 * The processor starts at 0xfffffffc and the code is first executed in the
10 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
14 #include <asm-offsets.h>
19 #include <ppc_asm.tmpl>
22 #include <asm/cache.h>
26 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
28 #define LAW_EN 0x80000000
30 #if defined(CONFIG_NAND_SPL) || \
31 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
35 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
36 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
41 * Set up GOT: Global Offset Table
43 * Use r12 to access the GOT
46 GOT_ENTRY(_GOT2_TABLE_)
47 GOT_ENTRY(_FIXUP_TABLE_)
51 GOT_ENTRY(_start_of_vectors)
52 GOT_ENTRY(_end_of_vectors)
53 GOT_ENTRY(transfer_to_handler)
58 GOT_ENTRY(__bss_start)
62 * e500 Startup -- after reset only the last 4KB of the effective
63 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
64 * section is located at THIS LAST page and basically does three
65 * things: clear some registers, set up exception tables and
66 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
67 * continue the boot procedure.
69 * Once the boot rom is mapped by TLB entries we can proceed
70 * with normal startup.
78 /* Enable debug exception */
83 * If we got an ePAPR device tree pointer passed in as r3, we need that
84 * later in cpu_init_early_f(). Save it to a safe register before we
85 * clobber it so that we can fetch it from there later.
89 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
96 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
102 /* Not a supported revision affected by erratum */
106 1: li r27,1 /* Remember for later that we have the erratum */
107 /* Erratum says set bits 55:60 to 001001 */
117 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
120 mfspr r3, SPRN_HDBCR0
122 mtspr SPRN_HDBCR0, r3
126 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
127 !defined(CONFIG_E6500)
128 /* ISBC uses L2 as stack.
129 * Disable L2 cache here so that u-boot can enable it later
130 * as part of it's normal flow
133 /* Check if L2 is enabled */
134 mfspr r3, SPRN_L2CSR0
136 ori r2, r2, L2CSR0_L2E@l
140 mfspr r3, SPRN_L2CSR0
142 lis r2,(L2CSR0_L2FL)@h
143 ori r2, r2, (L2CSR0_L2FL)@l
150 mfspr r3, SPRN_L2CSR0
154 mfspr r3, SPRN_L2CSR0
156 ori r2, r2, L2CSR0_L2E@l
166 /* clear registers/arrays not reset by hardware */
170 mtspr L1CSR0,r0 /* invalidate d-cache */
171 mtspr L1CSR1,r0 /* invalidate i-cache */
174 mtspr DBSR,r1 /* Clear all valid bits */
177 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
178 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
179 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
181 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
182 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
184 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
185 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
187 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
188 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
190 lis \scratch, \phy_high@h
191 ori \scratch, \scratch, \phy_high@l
199 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
200 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
201 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
203 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
204 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
206 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
207 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
209 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
210 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
212 lis \scratch, \phy_high@h
213 ori \scratch, \scratch, \phy_high@l
221 .macro delete_tlb1_entry esel scratch
222 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
223 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
233 .macro delete_tlb0_entry esel epn wimg scratch
234 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
235 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
239 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
240 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
248 /* Interrupt vectors do not fit in minimal SPL. */
249 #if !defined(MINIMAL_SPL)
250 /* Setup interrupt vectors */
251 lis r1,CONFIG_SYS_MONITOR_BASE@h
254 li r4,CriticalInput@l
255 mtspr IVOR0,r4 /* 0: Critical input */
257 mtspr IVOR1,r4 /* 1: Machine check */
259 mtspr IVOR2,r4 /* 2: Data storage */
261 mtspr IVOR3,r4 /* 3: Instruction storage */
263 mtspr IVOR4,r4 /* 4: External interrupt */
265 mtspr IVOR5,r4 /* 5: Alignment */
267 mtspr IVOR6,r4 /* 6: Program check */
268 li r4,FPUnavailable@l
269 mtspr IVOR7,r4 /* 7: floating point unavailable */
271 mtspr IVOR8,r4 /* 8: System call */
272 /* 9: Auxiliary processor unavailable(unsupported) */
274 mtspr IVOR10,r4 /* 10: Decrementer */
275 li r4,IntervalTimer@l
276 mtspr IVOR11,r4 /* 11: Interval timer */
277 li r4,WatchdogTimer@l
278 mtspr IVOR12,r4 /* 12: Watchdog timer */
280 mtspr IVOR13,r4 /* 13: Data TLB error */
281 li r4,InstructionTLBError@l
282 mtspr IVOR14,r4 /* 14: Instruction TLB error */
283 li r4,DebugBreakpoint@l
284 mtspr IVOR15,r4 /* 15: Debug */
287 /* Clear and set up some registers. */
290 mtspr DEC,r0 /* prevent dec exceptions */
291 mttbl r0 /* prevent fit & wdt exceptions */
293 mtspr TSR,r1 /* clear all timer exception status */
294 mtspr TCR,r0 /* disable all */
295 mtspr ESR,r0 /* clear exception syndrome register */
296 mtspr MCSR,r0 /* machine check syndrome register */
297 mtxer r0 /* clear integer exception register */
299 #ifdef CONFIG_SYS_BOOK3E_HV
300 mtspr MAS8,r0 /* make sure MAS8 is clear */
303 /* Enable Time Base and Select Time Base Clock */
304 lis r0,HID0_EMCP@h /* Enable machine check */
305 #if defined(CONFIG_ENABLE_36BIT_PHYS)
306 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
308 #ifndef CONFIG_E500MC
309 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
313 #if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
314 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
317 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
319 /* Set MBDD bit also */
320 ori r0, r0, HID1_MBDD@l
325 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
331 /* Enable Branch Prediction */
332 #if defined(CONFIG_BTB)
333 lis r0,BUCSR_ENABLE@h
334 ori r0,r0,BUCSR_ENABLE@l
338 #if defined(CONFIG_SYS_INIT_DBCR)
341 mtspr DBSR,r1 /* Clear all status bits */
342 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
343 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
347 #ifdef CONFIG_ARCH_MPC8569
348 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
349 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
351 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
352 * use address space which is more than 12bits, and it must be done in
353 * the 4K boot page. So we set this bit here.
356 /* create a temp mapping TLB0[0] for LBCR */
357 create_tlb0_entry 0, \
358 0, BOOKE_PAGESZ_4K, \
359 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
360 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
363 /* Set LBCR register */
364 lis r4,CONFIG_SYS_LBCR_ADDR@h
365 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
367 lis r5,CONFIG_SYS_LBC_LBCR@h
368 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
372 /* invalidate this temp TLB */
373 lis r4,CONFIG_SYS_LBC_ADDR@h
374 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
378 #endif /* CONFIG_ARCH_MPC8569 */
381 * Search for the TLB that covers the code we're executing, and shrink it
382 * so that it covers only this 4K page. That will ensure that any other
383 * TLB we create won't interfere with it. We assume that the TLB exists,
384 * which is why we don't check the Valid bit of MAS1. We also assume
387 * This is necessary, for example, when booting from the on-chip ROM,
388 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
390 bl nexti /* Find our address */
391 nexti: mflr r1 /* R1 = our PC */
393 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
396 tlbsx 0, r1 /* This must succeed */
398 mfspr r14, MAS0 /* Save ESEL for later */
399 rlwinm r14, r14, 16, 0xfff
401 /* Set the size of the TLB to 4KB */
404 andc r3, r3, r2 /* Clear the TSIZE bits */
405 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
406 oris r3, r3, MAS1_IPROT@h
410 * Set the base address of the TLB to our PC. We assume that
411 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
414 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
416 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
421 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
424 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
425 rlwinm r2, r2, 0, ~MAS2_I
429 mtspr MAS2, r2 /* Set the EPN to our PC base address */
434 mtspr MAS3, r2 /* Set the RPN to our PC base address */
441 * Clear out any other TLB entries that may exist, to avoid conflicts.
442 * Our TLB entry is in r14.
444 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
448 mfspr r4, SPRN_TLB1CFG
449 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
454 rlwinm r5, r3, 16, MAS0_ESEL_MSK
456 beq 2f /* skip the entry we're executing from */
458 oris r5, r5, MAS0_TLBSEL(1)@h
469 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
470 !defined(CONFIG_SECURE_BOOT)
472 * TLB entry for debuggging in AS1
473 * Create temporary TLB entry in AS0 to handle debug exception
474 * As on debug exception MSR is cleared i.e. Address space is changed
475 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
481 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
482 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
483 * and this window is outside of 4K boot window.
485 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
486 0, BOOKE_PAGESZ_4M, \
487 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
488 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
493 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
494 * because "nexti" will resize TLB to 4K
496 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
497 0, BOOKE_PAGESZ_256K, \
498 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
499 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
505 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
506 * location is not where we want it. This typically happens on a 36-bit
507 * system, where we want to move CCSR to near the top of 36-bit address space.
509 * To move CCSR, we create two temporary TLBs, one for the old location, and
510 * another for the new location. On CoreNet systems, we also need to create
511 * a special, temporary LAW.
513 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
514 * long-term TLBs, so we use TLB0 here.
516 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
518 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
519 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
524 * Create a TLB for the new location of CCSR. Register R8 is reserved
525 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
527 lis r8, CONFIG_SYS_CCSRBAR@h
528 ori r8, r8, CONFIG_SYS_CCSRBAR@l
529 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
530 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
531 create_tlb0_entry 0, \
532 0, BOOKE_PAGESZ_4K, \
533 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
534 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
535 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
537 * Create a TLB for the current location of CCSR. Register R9 is reserved
538 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
541 create_tlb0_entry 1, \
542 0, BOOKE_PAGESZ_4K, \
543 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
544 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
545 0, r3 /* The default CCSR address is always a 32-bit number */
549 * We have a TLB for what we think is the current (old) CCSR. Let's
550 * verify that, otherwise we won't be able to move it.
551 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
552 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
555 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
556 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
557 #ifdef CONFIG_FSL_CORENET
558 lwz r1, 4(r9) /* CCSRBARL */
560 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
567 * If the value we read from CCSRBARL is not what we expect, then
568 * enter an infinite loop. This will at least allow a debugger to
569 * halt execution and examine TLBs, etc. There's no point in going
573 bne infinite_debug_loop
575 #ifdef CONFIG_FSL_CORENET
577 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
578 #define LAW_SIZE_4K 0xb
579 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
580 #define CCSRAR_C 0x80000000 /* Commit */
584 * On CoreNet systems, we create the temporary LAW using a special LAW
585 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
587 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
588 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
589 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
590 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
591 lis r2, CCSRBAR_LAWAR@h
592 ori r2, r2, CCSRBAR_LAWAR@l
594 stw r0, 0xc00(r9) /* LAWBARH0 */
595 stw r1, 0xc04(r9) /* LAWBARL0 */
597 stw r2, 0xc08(r9) /* LAWAR0 */
600 * Read back from LAWAR to ensure the update is complete. e500mc
601 * cores also require an isync.
603 lwz r0, 0xc08(r9) /* LAWAR0 */
607 * Read the current CCSRBARH and CCSRBARL using load word instructions.
608 * Follow this with an isync instruction. This forces any outstanding
609 * accesses to configuration space to completion.
612 lwz r0, 0(r9) /* CCSRBARH */
613 lwz r0, 4(r9) /* CCSRBARL */
617 * Write the new values for CCSRBARH and CCSRBARL to their old
618 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
619 * has a new value written it loads a CCSRBARH shadow register. When
620 * the CCSRBARL is written, the CCSRBARH shadow register contents
621 * along with the CCSRBARL value are loaded into the CCSRBARH and
622 * CCSRBARL registers, respectively. Follow this with a sync
626 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
627 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
628 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
629 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
631 ori r2, r2, CCSRAR_C@l
633 stw r0, 0(r9) /* Write to CCSRBARH */
634 sync /* Make sure we write to CCSRBARH first */
635 stw r1, 4(r9) /* Write to CCSRBARL */
639 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
640 * Follow this with a sync instruction.
645 /* Delete the temporary LAW */
654 #else /* #ifdef CONFIG_FSL_CORENET */
658 * Read the current value of CCSRBAR using a load word instruction
659 * followed by an isync. This forces all accesses to configuration
666 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
667 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
668 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
670 /* Write the new value to CCSRBAR. */
671 lis r0, CCSRBAR_PHYS_RS12@h
672 ori r0, r0, CCSRBAR_PHYS_RS12@l
677 * The manual says to perform a load of an address that does not
678 * access configuration space or the on-chip SRAM using an existing TLB,
679 * but that doesn't appear to be necessary. We will do the isync,
685 * Read the contents of CCSRBAR from its new location, followed by
691 #endif /* #ifdef CONFIG_FSL_CORENET */
693 /* Delete the temporary TLBs */
695 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
696 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
698 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
700 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
703 * Create a TLB for the MMR location of CCSR
704 * to access L2CSR0 register
706 create_tlb0_entry 0, \
707 0, BOOKE_PAGESZ_4K, \
708 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
709 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
710 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
712 enable_l2_cluster_l2:
713 /* enable L2 cache */
714 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
715 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
716 li r4, 33 /* stash id */
718 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
719 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
721 stw r4, 0(r3) /* invalidate L2 */
722 /* Poll till the bits are cleared */
730 /* L2PE must be set before L2 cache is enabled */
731 lis r4, (L2CSR0_L2PE)@h
732 ori r4, r4, (L2CSR0_L2PE)@l
734 stw r4, 0(r3) /* enable L2 parity/ECC error checking */
735 /* Poll till the bit is set */
743 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
744 ori r4, r4, (L2CSR0_L2REP_MODE)@l
746 stw r4, 0(r3) /* enable L2 */
747 /* Poll till the bit is set */
756 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
760 * Enable the L1. On e6500, this has to be done
761 * after the L2 is up.
764 #ifdef CONFIG_SYS_CACHE_STASHING
765 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
770 /* Enable/invalidate the I-Cache */
771 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
772 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
779 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
780 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
785 andi. r1,r3,L1CSR1_ICE@l
788 /* Enable/invalidate the D-Cache */
789 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
790 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
797 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
798 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
803 andi. r1,r3,L1CSR0_DCE@l
805 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
806 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
807 #define LAW_SIZE_1M 0x13
808 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
814 * Create a TLB entry for CCSR
816 * We're executing out of TLB1 entry in r14, and that's the only
817 * TLB entry that exists. To allocate some TLB entries for our
818 * own use, flip a bit high enough that we won't flip it again
823 lis r0, MAS0_TLBSEL(1)@h
824 rlwimi r0, r8, 16, MAS0_ESEL_MSK
825 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
826 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
827 lis r7, CONFIG_SYS_CCSRBAR@h
828 ori r7, r7, CONFIG_SYS_CCSRBAR@l
829 ori r2, r7, MAS2_I|MAS2_G
830 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
831 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
832 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
833 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
844 /* Map DCSR temporarily to physical address zero */
846 lis r3, DCSRBAR_LAWAR@h
847 ori r3, r3, DCSRBAR_LAWAR@l
849 stw r0, 0xc00(r7) /* LAWBARH0 */
850 stw r0, 0xc04(r7) /* LAWBARL0 */
852 stw r3, 0xc08(r7) /* LAWAR0 */
854 /* Read back from LAWAR to ensure the update is complete. */
855 lwz r3, 0xc08(r7) /* LAWAR0 */
858 /* Create a TLB entry for DCSR at zero */
861 lis r0, MAS0_TLBSEL(1)@h
862 rlwimi r0, r9, 16, MAS0_ESEL_MSK
863 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
864 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
865 li r6, 0 /* DCSR effective address */
866 ori r2, r6, MAS2_I|MAS2_G
867 li r3, MAS3_SW|MAS3_SR
879 /* enable the timebase */
880 #define CTBENR 0xe2084
882 addis r4, r7, CTBENR@ha
888 .macro erratum_set_ccsr offset value
889 addis r3, r7, \offset@ha
891 addi r3, r3, \offset@l
896 .macro erratum_set_dcsr offset value
897 addis r3, r6, \offset@ha
899 addi r3, r3, \offset@l
904 erratum_set_dcsr 0xb0e08 0xe0201800
905 erratum_set_dcsr 0xb0e18 0xe0201800
906 erratum_set_dcsr 0xb0e38 0xe0400000
907 erratum_set_dcsr 0xb0008 0x00900000
908 erratum_set_dcsr 0xb0e40 0xe00a0000
909 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
910 #ifdef CONFIG_RAMBOOT_PBL
911 erratum_set_ccsr 0x10f00 0x495e5000
913 erratum_set_ccsr 0x10f00 0x415e5000
915 erratum_set_ccsr 0x11f00 0x415e5000
917 /* Make temp mapping uncacheable again, if it was initially */
922 rlwimi r4, r15, 0, MAS2_I
923 rlwimi r4, r15, 0, MAS2_G
930 /* Clear the cache */
931 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
932 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
942 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
943 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
953 /* Remove temporary mappings */
954 lis r0, MAS0_TLBSEL(1)@h
955 rlwimi r0, r9, 16, MAS0_ESEL_MSK
965 stw r3, 0xc08(r7) /* LAWAR0 */
969 lis r0, MAS0_TLBSEL(1)@h
970 rlwimi r0, r8, 16, MAS0_ESEL_MSK
981 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
983 /* Lock two cache lines into I-Cache */
985 mfspr r11, SPRN_L1CSR1
986 rlwinm r11, r11, 0, ~L1CSR1_ICUL
989 mtspr SPRN_L1CSR1, r11
1000 mfspr r11, SPRN_L1CSR1
1001 3: andi. r11, r11, L1CSR1_ICUL
1008 mfspr r11, SPRN_L1CSR1
1009 3: andi. r11, r11, L1CSR1_ICUL
1014 /* Inside a locked cacheline, wait a while, write, then wait a while */
1018 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1019 4: mfspr r5, SPRN_TBRL
1026 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
1027 4: mfspr r5, SPRN_TBRL
1034 * Fill out the rest of this cache line and the next with nops,
1035 * to ensure that nothing outside the locked area will be
1036 * fetched due to a branch.
1043 mfspr r11, SPRN_L1CSR1
1044 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1047 mtspr SPRN_L1CSR1, r11
1056 create_init_ram_area:
1057 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1058 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1061 /* create a temp mapping in AS=1 to the 4M boot window */
1062 create_tlb1_entry 15, \
1063 1, BOOKE_PAGESZ_4M, \
1064 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1065 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1068 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1069 /* create a temp mapping in AS = 1 for Flash mapping
1070 * created by PBL for ISBC code
1072 create_tlb1_entry 15, \
1073 1, BOOKE_PAGESZ_1M, \
1074 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1075 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1079 * For Targets without CONFIG_SPL like P3, P5
1080 * and for targets with CONFIG_SPL like T1, T2, T4, only for
1081 * u-boot-spl i.e. CONFIG_SPL_BUILD
1083 #elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \
1084 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
1085 /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
1086 * to L3 Address configured by PBL for ISBC code
1088 create_tlb1_entry 15, \
1089 1, BOOKE_PAGESZ_1M, \
1090 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1091 CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1096 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1097 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1099 create_tlb1_entry 15, \
1100 1, BOOKE_PAGESZ_1M, \
1101 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1102 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1106 /* create a temp mapping in AS=1 to the stack */
1107 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1108 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1109 create_tlb1_entry 14, \
1110 1, BOOKE_PAGESZ_16K, \
1111 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1112 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1113 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1116 create_tlb1_entry 14, \
1117 1, BOOKE_PAGESZ_16K, \
1118 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1119 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1123 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1124 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1126 ori r7,r7,switch_as@l
1133 /* L1 DCache is used for initial RAM */
1135 /* Allocate Initial RAM in data cache.
1137 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1138 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1141 /* cache size * 1024 / (2 * L1 line size) */
1142 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1147 #ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
1153 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1156 /* Jump out the last 4K page and continue to 'normal' start */
1157 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1158 /* We assume that we're already running at the address we're linked at */
1161 /* Calculate absolute address in FLASH and jump there */
1162 /*--------------------------------------------------------------*/
1163 lis r3,CONFIG_SYS_MONITOR_BASE@h
1164 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1165 addi r3,r3,_start_cont - _start
1173 .long 0x27051956 /* U-BOOT Magic Number */
1174 .globl version_string
1176 .ascii U_BOOT_VERSION_STRING, "\0"
1181 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1182 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1183 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1185 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
1186 #if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
1187 #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
1190 /* Leave 16+ byte for back chain termination and NULL return address */
1191 subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
1195 lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
1196 ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
1205 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
1206 lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
1207 ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
1209 addi r3,r3,16 /* Pre-relocation malloc area */
1210 stw r3,GD_MALLOC_BASE(r4)
1214 stw r0,0(r3) /* Terminate Back Chain */
1215 stw r0,+4(r3) /* NULL return address. */
1216 mr r1,r3 /* Transfer to SP(r1) */
1220 /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
1225 /* switch back to AS = 0 */
1226 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1227 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1231 bl cpu_init_f /* return boot_flag for calling board_init_f */
1235 /* NOTREACHED - board_init_f() does not return */
1238 .globl _start_of_vectors
1241 /* Critical input. */
1242 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1245 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1247 /* Data Storage exception. */
1248 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1250 /* Instruction Storage exception. */
1251 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1253 /* External Interrupt exception. */
1254 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1256 /* Alignment exception. */
1258 EXCEPTION_PROLOG(SRR0, SRR1)
1263 addi r3,r1,STACK_FRAME_OVERHEAD
1264 EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
1265 MSR_KERNEL, COPY_EE)
1267 /* Program check exception */
1269 EXCEPTION_PROLOG(SRR0, SRR1)
1270 addi r3,r1,STACK_FRAME_OVERHEAD
1271 EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
1272 MSR_KERNEL, COPY_EE)
1274 /* No FPU on MPC85xx. This exception is not supposed to happen.
1276 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1277 STD_EXCEPTION(0x0900, SystemCall, UnknownException)
1278 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1279 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1280 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1282 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1283 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1285 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1287 .globl _end_of_vectors
1291 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1294 * This code finishes saving the registers to the exception frame
1295 * and jumps to the appropriate handler for the exception.
1296 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1297 * r23 is the address of the handler.
1299 .globl transfer_to_handler
1300 transfer_to_handler:
1308 mtspr SPRG2,r22 /* r1 is now kernel sp */
1310 mtctr r23 /* virtual address of handler */
1315 mfmsr r28 /* Disable interrupts */
1319 SYNC /* Some chip revs need this... */
1334 lwz r2,_NIP(r1) /* Restore environment */
1348 .globl invalidate_icache
1351 ori r0,r0,L1CSR1_ICFI
1356 blr /* entire I cache */
1358 .globl invalidate_dcache
1361 ori r0,r0,L1CSR0_DCFI
1368 .globl icache_enable
1371 bl invalidate_icache
1375 ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
1376 oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
1381 .globl icache_disable
1385 ori r3,r3,L1CSR1_ICE
1391 .globl icache_status
1394 andi. r3,r3,L1CSR1_ICE
1397 .globl dcache_enable
1400 bl invalidate_dcache
1404 ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
1405 oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
1412 .globl dcache_disable
1416 ori r4,r4,L1CSR0_DCE
1422 .globl dcache_status
1425 andi. r3,r3,L1CSR0_DCE
1428 /*------------------------------------------------------------------------------- */
1430 /* Description: Input 8 bits */
1431 /*------------------------------------------------------------------------------- */
1437 /*------------------------------------------------------------------------------- */
1438 /* Function: out8 */
1439 /* Description: Output 8 bits */
1440 /*------------------------------------------------------------------------------- */
1447 /*------------------------------------------------------------------------------- */
1448 /* Function: out16 */
1449 /* Description: Output 16 bits */
1450 /*------------------------------------------------------------------------------- */
1457 /*------------------------------------------------------------------------------- */
1458 /* Function: out16r */
1459 /* Description: Byte reverse and output 16 bits */
1460 /*------------------------------------------------------------------------------- */
1467 /*------------------------------------------------------------------------------- */
1468 /* Function: out32 */
1469 /* Description: Output 32 bits */
1470 /*------------------------------------------------------------------------------- */
1477 /*------------------------------------------------------------------------------- */
1478 /* Function: out32r */
1479 /* Description: Byte reverse and output 32 bits */
1480 /*------------------------------------------------------------------------------- */
1487 /*------------------------------------------------------------------------------- */
1488 /* Function: in16 */
1489 /* Description: Input 16 bits */
1490 /*------------------------------------------------------------------------------- */
1496 /*------------------------------------------------------------------------------- */
1497 /* Function: in16r */
1498 /* Description: Input 16 bits and byte reverse */
1499 /*------------------------------------------------------------------------------- */
1505 /*------------------------------------------------------------------------------- */
1506 /* Function: in32 */
1507 /* Description: Input 32 bits */
1508 /*------------------------------------------------------------------------------- */
1514 /*------------------------------------------------------------------------------- */
1515 /* Function: in32r */
1516 /* Description: Input 32 bits and byte reverse */
1517 /*------------------------------------------------------------------------------- */
1522 #endif /* !MINIMAL_SPL */
1524 /*------------------------------------------------------------------------------*/
1527 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1535 #ifdef CONFIG_ENABLE_36BIT_PHYS
1539 #ifdef CONFIG_SYS_BOOK3E_HV
1549 * void relocate_code (addr_sp, gd, addr_moni)
1551 * This "function" does not return, instead it continues in RAM
1552 * after relocating the monitor code.
1556 * r5 = length in bytes
1557 * r6 = cachelinesize
1559 .globl relocate_code
1561 mr r1,r3 /* Set new stack pointer */
1562 mr r9,r4 /* Save copy of Init Data pointer */
1563 mr r10,r5 /* Save copy of Destination Address */
1566 #ifndef CONFIG_SPL_SKIP_RELOCATE
1567 mr r3,r5 /* Destination Address */
1568 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1569 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1570 lwz r5,GOT(__init_end)
1572 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1577 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1583 /* First our own GOT */
1585 /* the the one used by the C code */
1595 beq cr1,4f /* In place copy is not necessary */
1596 beq 7f /* Protect against 0 count */
1615 * Now flush the cache: note that we must start from a cache aligned
1616 * address. Otherwise we might miss one cache line.
1620 beq 7f /* Always flush prefetch queue in any case */
1628 sync /* Wait for all dcbst to complete on bus */
1634 7: sync /* Wait for all icbi to complete on bus */
1638 * We are done. Do not return, instead branch to second part of board
1639 * initialization, now running from RAM.
1642 addi r0,r10,in_ram - _start
1645 * As IVPR is going to point RAM address,
1646 * Make sure IVOR15 has valid opcode to support debugger
1651 * Re-point the IVPR at RAM
1656 blr /* NEVER RETURNS! */
1662 * Relocation Function, r12 point to got2+0x8000
1664 * Adjust got2 pointers, no need to check for 0, this code
1665 * already puts a few entries in the table.
1667 li r0,__got2_entries@sectoff@l
1668 la r3,GOT(_GOT2_TABLE_)
1669 lwz r11,GOT(_GOT2_TABLE_)
1681 * Now adjust the fixups and the pointers to the fixups
1682 * in case we need to move ourselves again.
1684 li r0,__fixup_entries@sectoff@l
1685 lwz r3,GOT(_FIXUP_TABLE_)
1701 * Now clear BSS segment
1703 lwz r3,GOT(__bss_start)
1704 lwz r4,GOT(__bss_end)
1717 mr r3,r9 /* Init Data pointer */
1718 mr r4,r10 /* Destination Address */
1723 * Copy exception vector code to low memory
1726 * r7: source address, r8: end address, r9: target address
1731 bl _GLOBAL_OFFSET_TABLE_-4
1734 /* Update IVORs as per relocation */
1737 lwz r4,CriticalInput@got(r12)
1738 mtspr IVOR0,r4 /* 0: Critical input */
1739 lwz r4,MachineCheck@got(r12)
1740 mtspr IVOR1,r4 /* 1: Machine check */
1741 lwz r4,DataStorage@got(r12)
1742 mtspr IVOR2,r4 /* 2: Data storage */
1743 lwz r4,InstStorage@got(r12)
1744 mtspr IVOR3,r4 /* 3: Instruction storage */
1745 lwz r4,ExtInterrupt@got(r12)
1746 mtspr IVOR4,r4 /* 4: External interrupt */
1747 lwz r4,Alignment@got(r12)
1748 mtspr IVOR5,r4 /* 5: Alignment */
1749 lwz r4,ProgramCheck@got(r12)
1750 mtspr IVOR6,r4 /* 6: Program check */
1751 lwz r4,FPUnavailable@got(r12)
1752 mtspr IVOR7,r4 /* 7: floating point unavailable */
1753 lwz r4,SystemCall@got(r12)
1754 mtspr IVOR8,r4 /* 8: System call */
1755 /* 9: Auxiliary processor unavailable(unsupported) */
1756 lwz r4,Decrementer@got(r12)
1757 mtspr IVOR10,r4 /* 10: Decrementer */
1758 lwz r4,IntervalTimer@got(r12)
1759 mtspr IVOR11,r4 /* 11: Interval timer */
1760 lwz r4,WatchdogTimer@got(r12)
1761 mtspr IVOR12,r4 /* 12: Watchdog timer */
1762 lwz r4,DataTLBError@got(r12)
1763 mtspr IVOR13,r4 /* 13: Data TLB error */
1764 lwz r4,InstructionTLBError@got(r12)
1765 mtspr IVOR14,r4 /* 14: Instruction TLB error */
1766 lwz r4,DebugBreakpoint@got(r12)
1767 mtspr IVOR15,r4 /* 15: Debug */
1772 .globl unlock_ram_in_cache
1773 unlock_ram_in_cache:
1774 /* invalidate the INIT_RAM section */
1775 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1776 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1779 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1782 #ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
1788 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1792 /* Invalidate the TLB entries for the cache */
1793 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1794 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1807 mfspr r3,SPRN_L1CFG0
1809 rlwinm r5,r3,9,3 /* Extract cache block size */
1810 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1811 * are currently defined.
1814 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1815 * log2(number of ways)
1817 slw r5,r4,r5 /* r5 = cache block size */
1819 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1820 mulli r7,r7,13 /* An 8-way cache will require 13
1825 /* save off HID0 and set DCFA */
1827 ori r9,r8,HID0_DCFA@l
1834 1: lwz r3,0(r4) /* Load... */
1842 1: dcbf 0,r4 /* ...and flush. */
1851 #endif /* !MINIMAL_SPL */