1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003 Motorola Inc.
6 * Xianghua Xiao, (X.Xiao@motorola.com)
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #include <ppc_asm.tmpl>
14 #include <linux/compiler.h>
15 #include <asm/processor.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
22 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24 /* --------------------------------------------------------------- */
26 void get_sys_info(sys_info_t *sys_info)
28 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
29 #ifdef CONFIG_FSL_CORENET
30 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
32 #ifdef CONFIG_HETROGENOUS_CLUSTERS
34 uint rcw_tmp1, rcw_tmp2;
36 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
37 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
39 __maybe_unused u32 svr;
41 const u8 core_cplx_PLL[16] = {
42 [ 0] = 0, /* CC1 PPL / 1 */
43 [ 1] = 0, /* CC1 PPL / 2 */
44 [ 2] = 0, /* CC1 PPL / 4 */
45 [ 4] = 1, /* CC2 PPL / 1 */
46 [ 5] = 1, /* CC2 PPL / 2 */
47 [ 6] = 1, /* CC2 PPL / 4 */
48 [ 8] = 2, /* CC3 PPL / 1 */
49 [ 9] = 2, /* CC3 PPL / 2 */
50 [10] = 2, /* CC3 PPL / 4 */
51 [12] = 3, /* CC4 PPL / 1 */
52 [13] = 3, /* CC4 PPL / 2 */
53 [14] = 3, /* CC4 PPL / 4 */
56 const u8 core_cplx_pll_div[16] = {
57 [ 0] = 1, /* CC1 PPL / 1 */
58 [ 1] = 2, /* CC1 PPL / 2 */
59 [ 2] = 4, /* CC1 PPL / 4 */
60 [ 4] = 1, /* CC2 PPL / 1 */
61 [ 5] = 2, /* CC2 PPL / 2 */
62 [ 6] = 4, /* CC2 PPL / 4 */
63 [ 8] = 1, /* CC3 PPL / 1 */
64 [ 9] = 2, /* CC3 PPL / 2 */
65 [10] = 4, /* CC3 PPL / 4 */
66 [12] = 1, /* CC4 PPL / 1 */
67 [13] = 2, /* CC4 PPL / 2 */
68 [14] = 4, /* CC4 PPL / 4 */
70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
72 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
75 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
76 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
79 sys_info->freq_systembus = sysclk;
80 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
82 unsigned int porsr1_sys_clk;
83 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
84 & FSL_DCFG_PORSR1_SYSCLK_MASK;
85 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
86 sys_info->diff_sysclk = 1;
88 sys_info->diff_sysclk = 0;
91 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
92 * are driven by separate DDR Refclock or single source
95 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
96 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
97 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
99 * For single source clocking, both ddrclock and sysclock
100 * are driven by differential sysclock.
102 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
103 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
106 #ifdef CONFIG_DDR_CLK_FREQ
107 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
109 sys_info->freq_ddrbus = sysclk;
112 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
114 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
115 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
117 if (mem_pll_rat == 0) {
118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
120 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
123 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
124 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
126 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
128 #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
129 defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
131 switch (SVR_SOC_VER(svr)) {
136 if (SVR_MAJ(svr) >= 2)
141 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
149 sys_info->freq_ddrbus *= mem_pll_rat;
151 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
153 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
154 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
156 freq_c_pll[i] = sysclk * ratio[i];
158 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
161 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
163 * As per CHASSIS2 architeture total 12 clusters are posible and
164 * Each cluster has up to 4 cores, sharing the same PLL selection.
165 * The cluster clock assignment is SoC defined.
167 * Total 4 clock groups are possible with 3 PLLs each.
168 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
169 * clock group B has 3, 4, 6 and so on.
171 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
172 * depends upon the SoC architeture. Same applies to other
173 * clock groups and clusters.
176 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
177 int cluster = fsl_qoriq_core_to_cluster(cpu);
178 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
180 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
181 cplx_pll += cc_group[cluster] - 1;
182 sys_info->freq_processor[cpu] =
183 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
186 #ifdef CONFIG_HETROGENOUS_CLUSTERS
187 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
188 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
189 u32 c_pll_sel = (in_be32
190 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
192 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
193 cplx_pll += cc_group[dsp_cluster] - 1;
194 sys_info->freq_processor_dsp[dsp_cpu] =
195 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
199 #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
200 defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
201 #define FM1_CLK_SEL 0xe0000000
202 #define FM1_CLK_SHIFT 29
203 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
204 #define FM1_CLK_SEL 0x00000007
205 #define FM1_CLK_SHIFT 0
207 #define PME_CLK_SEL 0xe0000000
208 #define PME_CLK_SHIFT 29
209 #define FM1_CLK_SEL 0x1c000000
210 #define FM1_CLK_SHIFT 26
212 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
213 #if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
214 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
216 rcw_tmp = in_be32(&gur->rcwsr[7]);
220 #ifdef CONFIG_SYS_DPAA_PME
221 #ifndef CONFIG_PME_PLAT_CLK_DIV
222 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
224 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
227 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
230 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
233 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
236 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
239 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
242 printf("Error: Unknown PME clock select!\n");
244 sys_info->freq_pme = sys_info->freq_systembus / 2;
249 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
254 #ifdef CONFIG_SYS_DPAA_QBMAN
255 #ifndef CONFIG_QBMAN_CLK_DIV
256 #define CONFIG_QBMAN_CLK_DIV 2
258 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
261 #if defined(CONFIG_SYS_MAPLE)
262 #define CPRI_CLK_SEL 0x1C000000
263 #define CPRI_CLK_SHIFT 26
264 #define CPRI_ALT_CLK_SEL 0x00007000
265 #define CPRI_ALT_CLK_SHIFT 12
267 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
268 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
269 /* For MAPLE and CPRI frequency */
270 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
272 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
273 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
276 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
277 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
280 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
281 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
284 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
285 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
288 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
289 >> CPRI_ALT_CLK_SHIFT) == 6) {
290 sys_info->freq_maple =
291 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
292 sys_info->freq_cpri =
293 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
295 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
296 >> CPRI_ALT_CLK_SHIFT) == 7) {
297 sys_info->freq_maple =
298 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
299 sys_info->freq_cpri =
300 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
304 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
305 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
308 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
309 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
312 printf("Error: Unknown MAPLE/CPRI clock select!\n");
315 /* For MAPLE ULB and eTVPE frequencies */
316 #define ULB_CLK_SEL 0x00000038
317 #define ULB_CLK_SHIFT 3
318 #define ETVPE_CLK_SEL 0x00000007
319 #define ETVPE_CLK_SHIFT 0
321 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
323 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
326 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
329 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
332 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
335 sys_info->freq_maple_ulb = sys_info->freq_systembus;
338 sys_info->freq_maple_ulb =
339 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
342 sys_info->freq_maple_ulb =
343 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
346 printf("Error: Unknown MAPLE ULB clock select!\n");
349 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
351 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
354 sys_info->freq_maple_etvpe =
355 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
358 sys_info->freq_maple_etvpe =
359 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
362 sys_info->freq_maple_etvpe =
363 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
366 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
369 sys_info->freq_maple_etvpe =
370 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
373 sys_info->freq_maple_etvpe =
374 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
377 printf("Error: Unknown MAPLE eTVPE clock select!\n");
382 #ifdef CONFIG_SYS_DPAA_FMAN
383 #ifndef CONFIG_FM_PLAT_CLK_DIV
384 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
386 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
389 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
392 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
395 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
398 sys_info->freq_fman[0] = sys_info->freq_systembus;
401 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
404 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
407 printf("Error: Unknown FMan1 clock select!\n");
409 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
412 #if (CONFIG_SYS_NUM_FMAN) == 2
413 #ifdef CONFIG_SYS_FM2_CLK
414 #define FM2_CLK_SEL 0x00000038
415 #define FM2_CLK_SHIFT 3
416 rcw_tmp = in_be32(&gur->rcwsr[15]);
417 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
419 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
422 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
425 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
428 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
431 sys_info->freq_fman[1] = sys_info->freq_systembus;
434 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
437 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
440 printf("Error: Unknown FMan2 clock select!\n");
442 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
446 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
448 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
452 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
453 #if defined(CONFIG_ARCH_T2080)
454 #define ESDHC_CLK_SEL 0x00000007
455 #define ESDHC_CLK_SHIFT 0
456 #define ESDHC_CLK_RCWSR 15
457 #else /* Support T1040 T1024 by now */
458 #define ESDHC_CLK_SEL 0xe0000000
459 #define ESDHC_CLK_SHIFT 29
460 #define ESDHC_CLK_RCWSR 7
462 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
463 switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
465 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
468 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
471 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
473 #if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
475 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
477 #if defined(CONFIG_ARCH_T2080)
479 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
483 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
486 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
490 sys_info->freq_sdhc = 0;
491 printf("Error: Unknown SDHC peripheral clock select!\n");
494 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
496 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
497 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
499 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
501 sys_info->freq_processor[cpu] =
502 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
504 #define PME_CLK_SEL 0x80000000
505 #define FM1_CLK_SEL 0x40000000
506 #define FM2_CLK_SEL 0x20000000
507 #define HWA_ASYNC_DIV 0x04000000
508 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
510 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
512 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
515 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
517 rcw_tmp = in_be32(&gur->rcwsr[7]);
519 #ifdef CONFIG_SYS_DPAA_PME
520 if (rcw_tmp & PME_CLK_SEL) {
521 if (rcw_tmp & HWA_ASYNC_DIV)
522 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
524 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
526 sys_info->freq_pme = sys_info->freq_systembus / 2;
530 #ifdef CONFIG_SYS_DPAA_FMAN
531 if (rcw_tmp & FM1_CLK_SEL) {
532 if (rcw_tmp & HWA_ASYNC_DIV)
533 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
535 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
537 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
539 #if (CONFIG_SYS_NUM_FMAN) == 2
540 if (rcw_tmp & FM2_CLK_SEL) {
541 if (rcw_tmp & HWA_ASYNC_DIV)
542 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
544 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
546 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
551 #ifdef CONFIG_SYS_DPAA_QBMAN
552 sys_info->freq_qman = sys_info->freq_systembus / 2;
555 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
558 sys_info->freq_qe = sys_info->freq_systembus / 2;
561 #else /* CONFIG_FSL_CORENET */
562 uint plat_ratio, e500_ratio, half_freq_systembus;
565 __maybe_unused u32 qe_ratio;
568 plat_ratio = (gur->porpllsr) & 0x0000003e;
570 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
572 /* Divide before multiply to avoid integer
573 * overflow for processor speeds above 2GHz */
574 half_freq_systembus = sys_info->freq_systembus/2;
575 for (i = 0; i < cpu_numcores(); i++) {
576 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
577 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
580 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
581 sys_info->freq_ddrbus = sys_info->freq_systembus;
583 #ifdef CONFIG_DDR_CLK_FREQ
585 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
586 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
587 if (ddr_ratio != 0x7)
588 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
593 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
594 sys_info->freq_qe = sys_info->freq_systembus;
596 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
597 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
598 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
602 #ifdef CONFIG_SYS_DPAA_FMAN
603 sys_info->freq_fman[0] = sys_info->freq_systembus;
606 #endif /* CONFIG_FSL_CORENET */
608 #if defined(CONFIG_FSL_LBC)
609 sys_info->freq_localbus = sys_info->freq_systembus /
610 CONFIG_SYS_FSL_LBC_CLK_DIV;
613 #if defined(CONFIG_FSL_IFC)
614 sys_info->freq_localbus = sys_info->freq_systembus /
615 CONFIG_SYS_FSL_IFC_CLK_DIV;
620 int get_clocks (void)
623 #ifdef CONFIG_ARCH_MPC8544
624 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
626 #if defined(CONFIG_CPM2)
627 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
630 /* set VCO = 4 * BRG */
631 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
632 sccr = cpm->im_cpm_intctl.sccr;
633 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
635 get_sys_info (&sys_info);
636 gd->cpu_clk = sys_info.freq_processor[0];
637 gd->bus_clk = sys_info.freq_systembus;
638 gd->mem_clk = sys_info.freq_ddrbus;
639 gd->arch.lbc_clk = sys_info.freq_localbus;
642 gd->arch.qe_clk = sys_info.freq_qe;
643 gd->arch.brg_clk = gd->arch.qe_clk / 2;
646 * The base clock for I2C depends on the actual SOC. Unfortunately,
647 * there is no pattern that can be used to determine the frequency, so
648 * the only choice is to look up the actual SOC number and use the value
649 * for that SOC. This information is taken from application note
652 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
653 defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
654 defined(CONFIG_ARCH_P1022)
655 gd->arch.i2c1_clk = sys_info.freq_systembus;
656 #elif defined(CONFIG_ARCH_MPC8544)
658 * On the 8544, the I2C clock is the same as the SEC clock. This can be
659 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
660 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
661 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
662 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
664 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
665 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
667 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
669 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
670 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
672 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
674 #if defined(CONFIG_FSL_ESDHC)
675 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
676 gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
678 #if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
679 gd->arch.sdhc_clk = gd->bus_clk;
681 gd->arch.sdhc_clk = gd->bus_clk / 2;
684 #endif /* defined(CONFIG_FSL_ESDHC) */
686 #if defined(CONFIG_CPM2)
687 gd->arch.vco_out = 2*sys_info.freq_systembus;
688 gd->arch.cpm_clk = gd->arch.vco_out / 2;
689 gd->arch.scc_clk = gd->arch.vco_out / 4;
690 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
693 if(gd->cpu_clk != 0) return (0);
698 /********************************************
700 * return system bus freq in Hz
701 *********************************************/
702 ulong get_bus_freq (ulong dummy)
707 /********************************************
709 * return ddr bus freq in Hz
710 *********************************************/
711 ulong get_ddr_freq (ulong dummy)