2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <ppc_asm.tmpl>
15 #include <linux/compiler.h>
16 #include <asm/processor.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23 #define CONFIG_SYS_FSL_NUM_CC_PLLS 6
25 /* --------------------------------------------------------------- */
27 void get_sys_info(sys_info_t *sys_info)
29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
34 #ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
41 const u8 core_cplx_PLL[16] = {
42 [ 0] = 0, /* CC1 PPL / 1 */
43 [ 1] = 0, /* CC1 PPL / 2 */
44 [ 2] = 0, /* CC1 PPL / 4 */
45 [ 4] = 1, /* CC2 PPL / 1 */
46 [ 5] = 1, /* CC2 PPL / 2 */
47 [ 6] = 1, /* CC2 PPL / 4 */
48 [ 8] = 2, /* CC3 PPL / 1 */
49 [ 9] = 2, /* CC3 PPL / 2 */
50 [10] = 2, /* CC3 PPL / 4 */
51 [12] = 3, /* CC4 PPL / 1 */
52 [13] = 3, /* CC4 PPL / 2 */
53 [14] = 3, /* CC4 PPL / 4 */
56 const u8 core_cplx_pll_div[16] = {
57 [ 0] = 1, /* CC1 PPL / 1 */
58 [ 1] = 2, /* CC1 PPL / 2 */
59 [ 2] = 4, /* CC1 PPL / 4 */
60 [ 4] = 1, /* CC2 PPL / 1 */
61 [ 5] = 2, /* CC2 PPL / 2 */
62 [ 6] = 4, /* CC2 PPL / 4 */
63 [ 8] = 1, /* CC3 PPL / 1 */
64 [ 9] = 2, /* CC3 PPL / 2 */
65 [10] = 4, /* CC3 PPL / 4 */
66 [12] = 1, /* CC4 PPL / 1 */
67 [13] = 2, /* CC4 PPL / 2 */
68 [14] = 4, /* CC4 PPL / 4 */
70 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
71 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
77 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
81 sys_info->freq_systembus = sysclk;
82 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
85 * are driven by separate DDR Refclock or single source
88 single_src = (in_be32(&gur->rcwsr[5]) >>
89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
92 * For single source clocking, both ddrclock and syclock
93 * are driven by differential sysclock.
95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
96 printf("Single Source Clock Configuration\n");
97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
100 #ifdef CONFIG_DDR_CLK_FREQ
101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
103 sys_info->freq_ddrbus = sysclk;
106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
114 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
115 if (SVR_MAJ(get_svr()) >= 2)
119 sys_info->freq_ddrbus *= mem_pll_rat;
121 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
123 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
124 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
126 freq_c_pll[i] = sysclk * ratio[i];
128 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
130 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
132 * As per CHASSIS2 architeture total 12 clusters are posible and
133 * Each cluster has up to 4 cores, sharing the same PLL selection.
134 * The cluster clock assignment is SoC defined.
136 * Total 4 clock groups are possible with 3 PLLs each.
137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
138 * clock group B has 3, 4, 6 and so on.
140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
141 * depends upon the SoC architeture. Same applies to other
142 * clock groups and clusters.
145 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
146 int cluster = fsl_qoriq_core_to_cluster(cpu);
147 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
149 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
150 cplx_pll += cc_group[cluster] - 1;
151 sys_info->freq_processor[cpu] =
152 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
154 #if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
155 #define FM1_CLK_SEL 0xe0000000
156 #define FM1_CLK_SHIFT 29
158 #define PME_CLK_SEL 0xe0000000
159 #define PME_CLK_SHIFT 29
160 #define FM1_CLK_SEL 0x1c000000
161 #define FM1_CLK_SHIFT 26
163 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
164 rcw_tmp = in_be32(&gur->rcwsr[7]);
167 #ifdef CONFIG_SYS_DPAA_PME
168 #ifndef CONFIG_PME_PLAT_CLK_DIV
169 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
171 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
174 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
177 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
180 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
183 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
186 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
189 printf("Error: Unknown PME clock select!\n");
191 sys_info->freq_pme = sys_info->freq_systembus / 2;
196 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
201 #ifdef CONFIG_SYS_DPAA_QBMAN
202 sys_info->freq_qman = sys_info->freq_systembus / 2;
205 #ifdef CONFIG_SYS_DPAA_FMAN
206 #ifndef CONFIG_FM_PLAT_CLK_DIV
207 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
209 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
212 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
215 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
218 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
221 sys_info->freq_fman[0] = sys_info->freq_systembus;
224 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
227 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
230 printf("Error: Unknown FMan1 clock select!\n");
232 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
235 #if (CONFIG_SYS_NUM_FMAN) == 2
236 #ifdef CONFIG_SYS_FM2_CLK
237 #define FM2_CLK_SEL 0x00000038
238 #define FM2_CLK_SHIFT 3
239 rcw_tmp = in_be32(&gur->rcwsr[15]);
240 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
242 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
245 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
248 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
251 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
254 sys_info->freq_fman[1] = sys_info->freq_systembus;
257 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
260 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
263 printf("Error: Unknown FMan2 clock select!\n");
265 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
269 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
271 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
275 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
277 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
278 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
280 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
282 sys_info->freq_processor[cpu] =
283 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
285 #define PME_CLK_SEL 0x80000000
286 #define FM1_CLK_SEL 0x40000000
287 #define FM2_CLK_SEL 0x20000000
288 #define HWA_ASYNC_DIV 0x04000000
289 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
291 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
293 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
296 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
298 rcw_tmp = in_be32(&gur->rcwsr[7]);
300 #ifdef CONFIG_SYS_DPAA_PME
301 if (rcw_tmp & PME_CLK_SEL) {
302 if (rcw_tmp & HWA_ASYNC_DIV)
303 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
305 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
307 sys_info->freq_pme = sys_info->freq_systembus / 2;
311 #ifdef CONFIG_SYS_DPAA_FMAN
312 if (rcw_tmp & FM1_CLK_SEL) {
313 if (rcw_tmp & HWA_ASYNC_DIV)
314 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
316 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
318 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
320 #if (CONFIG_SYS_NUM_FMAN) == 2
321 if (rcw_tmp & FM2_CLK_SEL) {
322 if (rcw_tmp & HWA_ASYNC_DIV)
323 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
325 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
327 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
332 #ifdef CONFIG_SYS_DPAA_QBMAN
333 sys_info->freq_qman = sys_info->freq_systembus / 2;
336 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
338 #else /* CONFIG_FSL_CORENET */
339 uint plat_ratio, e500_ratio, half_freq_systembus;
342 __maybe_unused u32 qe_ratio;
345 plat_ratio = (gur->porpllsr) & 0x0000003e;
347 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
349 /* Divide before multiply to avoid integer
350 * overflow for processor speeds above 2GHz */
351 half_freq_systembus = sys_info->freq_systembus/2;
352 for (i = 0; i < cpu_numcores(); i++) {
353 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
354 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
357 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
358 sys_info->freq_ddrbus = sys_info->freq_systembus;
360 #ifdef CONFIG_DDR_CLK_FREQ
362 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
363 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
364 if (ddr_ratio != 0x7)
365 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
370 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
371 sys_info->freq_qe = sys_info->freq_systembus;
373 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
374 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
375 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
379 #ifdef CONFIG_SYS_DPAA_FMAN
380 sys_info->freq_fman[0] = sys_info->freq_systembus;
383 #endif /* CONFIG_FSL_CORENET */
385 #if defined(CONFIG_FSL_LBC)
387 #if defined(CONFIG_SYS_LBC_LCRR)
388 /* We will program LCRR to this value later */
389 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
391 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
393 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
394 #if defined(CONFIG_FSL_CORENET)
395 /* If this is corenet based SoC, bit-representation
396 * for four times the clock divider values.
399 #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
400 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
402 * Yes, the entire PQ38 family use the same
403 * bit-representation for twice the clock divider values.
407 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
409 /* In case anyone cares what the unknown value is */
410 sys_info->freq_localbus = lcrr_div;
414 #if defined(CONFIG_FSL_IFC)
415 ccr = in_be32(&ifc_regs->ifc_ccr);
416 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
418 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
423 int get_clocks (void)
426 #ifdef CONFIG_MPC8544
427 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
429 #if defined(CONFIG_CPM2)
430 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
433 /* set VCO = 4 * BRG */
434 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
435 sccr = cpm->im_cpm_intctl.sccr;
436 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
438 get_sys_info (&sys_info);
439 gd->cpu_clk = sys_info.freq_processor[0];
440 gd->bus_clk = sys_info.freq_systembus;
441 gd->mem_clk = sys_info.freq_ddrbus;
442 gd->arch.lbc_clk = sys_info.freq_localbus;
445 gd->arch.qe_clk = sys_info.freq_qe;
446 gd->arch.brg_clk = gd->arch.qe_clk / 2;
449 * The base clock for I2C depends on the actual SOC. Unfortunately,
450 * there is no pattern that can be used to determine the frequency, so
451 * the only choice is to look up the actual SOC number and use the value
452 * for that SOC. This information is taken from application note
455 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
456 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
457 defined(CONFIG_P1022)
458 gd->arch.i2c1_clk = sys_info.freq_systembus;
459 #elif defined(CONFIG_MPC8544)
461 * On the 8544, the I2C clock is the same as the SEC clock. This can be
462 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
463 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
464 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
465 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
467 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
468 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
470 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
472 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
473 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
475 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
477 #if defined(CONFIG_FSL_ESDHC)
478 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
479 defined(CONFIG_P1014)
480 gd->arch.sdhc_clk = gd->bus_clk;
482 gd->arch.sdhc_clk = gd->bus_clk / 2;
484 #endif /* defined(CONFIG_FSL_ESDHC) */
486 #if defined(CONFIG_CPM2)
487 gd->arch.vco_out = 2*sys_info.freq_systembus;
488 gd->arch.cpm_clk = gd->arch.vco_out / 2;
489 gd->arch.scc_clk = gd->arch.vco_out / 4;
490 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
493 if(gd->cpu_clk != 0) return (0);
498 /********************************************
500 * return system bus freq in Hz
501 *********************************************/
502 ulong get_bus_freq (ulong dummy)
507 /********************************************
509 * return ddr bus freq in Hz
510 *********************************************/
511 ulong get_ddr_freq (ulong dummy)