1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * Kumar Gala <kumar.gala@freescale.com>
7 #include <asm-offsets.h>
11 #include <ppc_asm.tmpl>
14 #include <asm/cache.h>
17 /* To boot secondary cpus, we need a place for them to start up.
18 * Normally, they start at 0xfffffffc, but that's usually the
19 * firmware, and we don't want to have to run the firmware again.
20 * Instead, the primary cpu will set the BPTR to point here to
21 * this page. We then set up the core, and head to
22 * start_secondary. Note that this means that the code below
23 * must never exceed 1023 instructions (the branch at the end
24 * would then be the 1024th).
26 .globl __secondary_start_page
28 __secondary_start_page:
29 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
36 /* First do some preliminary setup */
37 lis r3, HID0_EMCP@h /* enable machine check */
39 ori r3,r3,HID0_TBEN@l /* enable Timebase */
41 #ifdef CONFIG_PHYS_64BIT
42 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
47 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
50 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
52 /* Set MBDD bit also */
53 ori r3, r3, HID1_MBDD@l
58 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
64 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
67 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
71 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
72 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
77 /* Not a supported revision affected by erratum */
80 1: /* Erratum says set bits 55:60 to 001001 */
91 /* Enable branch prediction */
93 ori r3,r3,BUCSR_ENABLE@l
101 /* Enable/invalidate the I-Cache */
102 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
103 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
110 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
111 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
116 andi. r1,r3,L1CSR1_ICE@l
119 /* Enable/invalidate the D-Cache */
120 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
121 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
128 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
129 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
134 andi. r1,r3,L1CSR0_DCE@l
137 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
139 /* get our PIR to figure out our table entry */
140 lis r3,toreset(__spin_table_addr)@h
141 ori r3,r3,toreset(__spin_table_addr)@l
145 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
147 * PIR definition for Chassis 2
148 * 0-17 Reserved (logic 0s)
149 * 18-19 CHIP_ID, 2'b00 - SoC 1
150 * all others - reserved
151 * 20-24 CLUSTER_ID 5'b00000 - CCM 1
152 * all others - reserved
153 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
157 * 27-28 CORE_ID 2'b00 - core 0
161 * 29-31 THREAD_ID 3'b000 - thread 0
164 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
165 * and clusters by 0x20.
167 * We renumber PIR so that all threads in the system are consecutive.
170 rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
171 srwi r10,r0,5 /* r10 = cluster */
173 mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
174 add r5,r5,r8 /* for spin table index */
175 mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
176 #elif defined(CONFIG_E500MC)
177 rlwinm r4,r0,27,27,31
185 * r10 has the base address for the entry.
186 * we cannot access it yet before setting up a new TLB
188 slwi r8,r5,6 /* spin table is padded to 64 byte */
191 mtspr SPRN_PIR,r4 /* write to PIR register */
193 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
195 clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
198 #ifdef CONFIG_SYS_CACHE_STASHING
199 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
204 #endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
206 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
207 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
209 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
210 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
211 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
214 rlwinm r6,r3,24,~0x800 /* clear E bit */
217 ori r5,r5,SVR_P4080@l
226 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
227 lis r3,toreset(enable_cpu_a011_workaround)@ha
228 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
233 oris r3,r3,(L1CSR2_DCWS)@h
238 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
240 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
241 * write shadow mode. This code should run after other code setting
245 andis. r3,r3,(L1CSR2_DCWS)@h
247 mfspr r3, SPRN_HDBCR0
249 mtspr SPRN_HDBCR0, r3
253 #ifdef CONFIG_BACKSIDE_L2_CACHE
254 /* skip L2 setup on P2040/P2040E as they have no L2 */
256 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
259 ori r3,r3,SVR_P2040@l
263 /* Enable/invalidate the L2 cache */
265 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
266 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
273 #ifdef CONFIG_SYS_CACHE_STASHING
274 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
279 lis r3,CONFIG_SYS_INIT_L2CSR0@h
280 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
285 andis. r1,r3,L2CSR0_L2E@h
289 /* setup mapping for the spin table, WIMGE=0b00100 */
290 lis r13,toreset(__spin_table_addr)@h
291 ori r13,r13,toreset(__spin_table_addr)@l
294 rlwinm r13,r13,0,0,19
296 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
298 lis r11,(MAS1_VALID|MAS1_IPROT)@h
299 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
301 oris r11,r13,(MAS2_M|MAS2_G)@h
302 ori r11,r13,(MAS2_M|MAS2_G)@l
304 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
305 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
312 * __bootpg_addr has the address of __second_half_boot_page
313 * jump there in AS=1 space with cache enabled
315 lis r13,toreset(__bootpg_addr)@h
316 ori r13,r13,toreset(__bootpg_addr)@l
320 ori r12,r13,MSR_IS|MSR_DS@l
325 * Allocate some space for the SDRAM address of the bootpg.
326 * This variable has to be in the boot page so that it can
327 * be accessed by secondary cores when they come out of reset.
329 .align L1_CACHE_SHIFT
334 .global __spin_table_addr
339 * This variable is set by cpu_init_r() after parsing hwconfig
340 * to enable workaround for erratum NMG_CPU_A011.
342 .align L1_CACHE_SHIFT
343 .global enable_cpu_a011_workaround
344 enable_cpu_a011_workaround:
347 /* Fill in the empty space. The actual reset vector is
348 * the last word of the page */
349 __secondary_start_code_end:
350 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
351 __secondary_reset_vector:
352 b __secondary_start_page
355 /* this is a separated page for the spin table and cacheable boot code */
356 .align L1_CACHE_SHIFT
357 .global __second_half_boot_page
358 __second_half_boot_page:
359 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
360 lis r3,(spin_table_compat - __second_half_boot_page)@h
361 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
362 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
366 #define ENTRY_ADDR_UPPER 0
367 #define ENTRY_ADDR_LOWER 4
368 #define ENTRY_R3_UPPER 8
369 #define ENTRY_R3_LOWER 12
370 #define ENTRY_RESV 16
372 #define ENTRY_SIZE 64
375 * r10 has the base address of the spin table.
376 * spin table is defined as
378 * uint64_t entry_addr;
383 * we pad this struct to 64 bytes so each entry is in its own cacheline
388 stw r3,ENTRY_ADDR_UPPER(r10)
389 stw r3,ENTRY_R3_UPPER(r10)
390 stw r4,ENTRY_R3_LOWER(r10)
391 stw r3,ENTRY_RESV(r10)
392 stw r4,ENTRY_PIR(r10)
394 stw r8,ENTRY_ADDR_LOWER(r10)
396 /* spin waiting for addr */
399 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
400 * memory. Old OS may not work with this change. A patch is waiting to be
401 * accepted for Linux kernel. Other OS needs similar fix to spin table.
402 * For OSes with old spin table code, we can enable this temporary fix by
403 * setting environmental variable "spin_table_compat". For new OSes, set
404 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
405 * and related code. For now, it is enabled by default.
407 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
414 lwz r4,ENTRY_ADDR_LOWER(r10)
419 /* get the upper bits of the addr */
420 lwz r11,ENTRY_ADDR_UPPER(r10)
422 /* setup branch addr */
425 /* mark the entry as released */
427 stw r8,ENTRY_ADDR_LOWER(r10)
429 /* mask by ~64M to setup our tlb we will jump to */
433 * setup r3, r4, r5, r6, r7, r8, r9
434 * r3 contains the value to put in the r3 register at secondary cpu
435 * entry. The high 32-bits are ignored on 32-bit chip implementations.
436 * 64-bit chip implementations however shall load all 64-bits
438 #ifdef CONFIG_SYS_PPC64
439 ld r3,ENTRY_R3_UPPER(r10)
441 lwz r3,ENTRY_R3_LOWER(r10)
446 lis r7,(64*1024*1024)@h
450 /* load up the pir */
451 lwz r0,ENTRY_PIR(r10)
454 stw r0,ENTRY_PIR(r10)
458 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
459 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
460 * second mapping that maps addr 1:1 for 64M, and then we jump to
463 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
465 lis r10,(MAS1_VALID|MAS1_IPROT)@h
466 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
468 /* WIMGE = 0b00000 for now */
470 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
472 #ifdef CONFIG_ENABLE_36BIT_PHYS
477 /* Now we have another mapping for this page, so we jump to that
487 .space CONFIG_MAX_CPUS*ENTRY_SIZE
489 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
490 .align L1_CACHE_SHIFT
491 .global spin_table_compat
498 .space 4096 - (__spin_table_end - __spin_table)