2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
13 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
15 #include <ppc_asm.tmpl>
18 #include <asm/cache.h>
21 /* To boot secondary cpus, we need a place for them to start up.
22 * Normally, they start at 0xfffffffc, but that's usually the
23 * firmware, and we don't want to have to run the firmware again.
24 * Instead, the primary cpu will set the BPTR to point here to
25 * this page. We then set up the core, and head to
26 * start_secondary. Note that this means that the code below
27 * must never exceed 1023 instructions (the branch at the end
28 * would then be the 1024th).
30 .globl __secondary_start_page
32 __secondary_start_page:
33 /* First do some preliminary setup */
34 lis r3, HID0_EMCP@h /* enable machine check */
36 ori r3,r3,HID0_TBEN@l /* enable Timebase */
38 #ifdef CONFIG_PHYS_64BIT
39 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
44 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
47 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
49 /* Set MBDD bit also */
50 ori r3, r3, HID1_MBDD@l
55 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
61 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
64 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
68 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
69 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
74 /* Not a supported revision affected by erratum */
77 1: /* Erratum says set bits 55:60 to 001001 */
88 /* Enable branch prediction */
90 ori r3,r3,BUCSR_ENABLE@l
98 /* Enable/invalidate the I-Cache */
99 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
100 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
107 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
108 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
113 andi. r1,r3,L1CSR1_ICE@l
116 /* Enable/invalidate the D-Cache */
117 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
118 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
125 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
126 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
131 andi. r1,r3,L1CSR0_DCE@l
134 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
136 /* get our PIR to figure out our table entry */
137 lis r3,toreset(__spin_table_addr)@h
138 ori r3,r3,toreset(__spin_table_addr)@l
142 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
144 * PIR definition for Chassis 2
145 * 0-17 Reserved (logic 0s)
146 * 18-19 CHIP_ID, 2'b00 - SoC 1
147 * all others - reserved
148 * 20-24 CLUSTER_ID 5'b00000 - CCM 1
149 * all others - reserved
150 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
154 * 27-28 CORE_ID 2'b00 - core 0
158 * 29-31 THREAD_ID 3'b000 - thread 0
161 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
162 * and clusters by 0x20.
164 * We renumber PIR so that all threads in the system are consecutive.
167 rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
168 srwi r10,r0,5 /* r10 = cluster */
170 mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
171 add r5,r5,r8 /* for spin table index */
172 mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
173 #elif defined(CONFIG_E500MC)
174 rlwinm r4,r0,27,27,31
182 * r10 has the base address for the entry.
183 * we cannot access it yet before setting up a new TLB
185 slwi r8,r5,6 /* spin table is padded to 64 byte */
188 mtspr SPRN_PIR,r4 /* write to PIR register */
190 #ifdef CONFIG_SYS_CACHE_STASHING
191 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
197 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
198 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
200 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
201 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
202 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
205 rlwinm r6,r3,24,~0x800 /* clear E bit */
208 ori r5,r5,SVR_P4080@l
217 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
218 lis r3,toreset(enable_cpu_a011_workaround)@ha
219 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
224 oris r3,r3,(L1CSR2_DCWS)@h
229 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
231 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
232 * write shadow mode. This code should run after other code setting
236 andis. r3,r3,(L1CSR2_DCWS)@h
238 mfspr r3, SPRN_HDBCR0
240 mtspr SPRN_HDBCR0, r3
244 #ifdef CONFIG_BACKSIDE_L2_CACHE
245 /* skip L2 setup on P2040/P2040E as they have no L2 */
247 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
250 ori r3,r3,SVR_P2040@l
254 /* Enable/invalidate the L2 cache */
256 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
257 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
264 #ifdef CONFIG_SYS_CACHE_STASHING
265 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
270 lis r3,CONFIG_SYS_INIT_L2CSR0@h
271 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
276 andis. r1,r3,L2CSR0_L2E@h
280 /* setup mapping for the spin table, WIMGE=0b00100 */
281 lis r13,toreset(__spin_table_addr)@h
282 ori r13,r13,toreset(__spin_table_addr)@l
285 rlwinm r13,r13,0,0,19
287 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
289 lis r11,(MAS1_VALID|MAS1_IPROT)@h
290 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
292 oris r11,r13,(MAS2_M|MAS2_G)@h
293 ori r11,r13,(MAS2_M|MAS2_G)@l
295 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
296 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
303 * __bootpg_addr has the address of __second_half_boot_page
304 * jump there in AS=1 space with cache enabled
306 lis r13,toreset(__bootpg_addr)@h
307 ori r13,r13,toreset(__bootpg_addr)@l
311 ori r12,r13,MSR_IS|MSR_DS@l
316 * Allocate some space for the SDRAM address of the bootpg.
317 * This variable has to be in the boot page so that it can
318 * be accessed by secondary cores when they come out of reset.
320 .align L1_CACHE_SHIFT
325 .global __spin_table_addr
330 * This variable is set by cpu_init_r() after parsing hwconfig
331 * to enable workaround for erratum NMG_CPU_A011.
333 .align L1_CACHE_SHIFT
334 .global enable_cpu_a011_workaround
335 enable_cpu_a011_workaround:
338 /* Fill in the empty space. The actual reset vector is
339 * the last word of the page */
340 __secondary_start_code_end:
341 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
342 __secondary_reset_vector:
343 b __secondary_start_page
346 /* this is a separated page for the spin table and cacheable boot code */
347 .align L1_CACHE_SHIFT
348 .global __second_half_boot_page
349 __second_half_boot_page:
350 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
351 lis r3,(spin_table_compat - __second_half_boot_page)@h
352 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
353 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
357 #define ENTRY_ADDR_UPPER 0
358 #define ENTRY_ADDR_LOWER 4
359 #define ENTRY_R3_UPPER 8
360 #define ENTRY_R3_LOWER 12
361 #define ENTRY_RESV 16
363 #define ENTRY_SIZE 64
366 * r10 has the base address of the spin table.
367 * spin table is defined as
369 * uint64_t entry_addr;
374 * we pad this struct to 64 bytes so each entry is in its own cacheline
379 stw r3,ENTRY_ADDR_UPPER(r10)
380 stw r3,ENTRY_R3_UPPER(r10)
381 stw r4,ENTRY_R3_LOWER(r10)
382 stw r3,ENTRY_RESV(r10)
383 stw r4,ENTRY_PIR(r10)
385 stw r8,ENTRY_ADDR_LOWER(r10)
387 /* spin waiting for addr */
390 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
391 * memory. Old OS may not work with this change. A patch is waiting to be
392 * accepted for Linux kernel. Other OS needs similar fix to spin table.
393 * For OSes with old spin table code, we can enable this temporary fix by
394 * setting environmental variable "spin_table_compat". For new OSes, set
395 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
396 * and related code. For now, it is enabled by default.
398 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
405 lwz r4,ENTRY_ADDR_LOWER(r10)
410 /* setup IVORs to match fixed offsets */
411 #include "fixed_ivor.S"
413 /* get the upper bits of the addr */
414 lwz r11,ENTRY_ADDR_UPPER(r10)
416 /* setup branch addr */
419 /* mark the entry as released */
421 stw r8,ENTRY_ADDR_LOWER(r10)
423 /* mask by ~64M to setup our tlb we will jump to */
427 * setup r3, r4, r5, r6, r7, r8, r9
428 * r3 contains the value to put in the r3 register at secondary cpu
429 * entry. The high 32-bits are ignored on 32-bit chip implementations.
430 * 64-bit chip implementations however shall load all 64-bits
432 #ifdef CONFIG_SYS_PPC64
433 ld r3,ENTRY_R3_UPPER(r10)
435 lwz r3,ENTRY_R3_LOWER(r10)
440 lis r7,(64*1024*1024)@h
444 /* load up the pir */
445 lwz r0,ENTRY_PIR(r10)
448 stw r0,ENTRY_PIR(r10)
452 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
453 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
454 * second mapping that maps addr 1:1 for 64M, and then we jump to
457 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
459 lis r10,(MAS1_VALID|MAS1_IPROT)@h
460 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
462 /* WIMGE = 0b00000 for now */
464 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
466 #ifdef CONFIG_ENABLE_36BIT_PHYS
471 /* Now we have another mapping for this page, so we jump to that
481 .space CONFIG_MAX_CPUS*ENTRY_SIZE
483 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
484 .align L1_CACHE_SHIFT
485 .global spin_table_compat
492 .space 4096 - (__spin_table_end - __spin_table)