1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004 Freescale Semiconductor.
4 * Copyright (C) 2003 Motorola Inc.
5 * Xianghua Xiao (x.xiao@motorola.com)
9 * PCI Configuration space access support for MPC85xx PCI Bridge
12 #include <asm/cpm_85xx.h>
15 #if !defined(CONFIG_FSL_PCI_INIT)
17 #ifndef CONFIG_SYS_PCI1_MEM_BUS
18 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
21 #ifndef CONFIG_SYS_PCI1_IO_BUS
22 #define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
25 #ifndef CONFIG_SYS_PCI2_MEM_BUS
26 #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
29 #ifndef CONFIG_SYS_PCI2_IO_BUS
30 #define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
33 static struct pci_controller *pci_hose;
36 pci_mpc85xx_init(struct pci_controller *board_hose)
41 volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
42 #ifdef CONFIG_MPC85XX_PCI2
43 volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
45 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
46 struct pci_controller * hose;
48 pci_hose = board_hose;
52 hose->first_busno = 0;
53 hose->last_busno = 0xff;
55 pci_setup_indirect(hose,
56 (CONFIG_SYS_IMMR+0x8000),
57 (CONFIG_SYS_IMMR+0x8004));
62 dev = PCI_BDF(hose->first_busno, 0, 0);
63 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
64 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
65 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
68 * Clear non-reserved bits in status register.
70 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
72 if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
74 if (CONFIG_SYS_CLK_FREQ < 66000000)
75 printf("PCI-X will only work at 66 MHz\n");
77 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
78 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
79 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
82 pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
83 pcix->potear1 = 0x00000000;
84 pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
85 pcix->powbear1 = 0x00000000;
86 pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
87 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
89 pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
90 pcix->potear2 = 0x00000000;
91 pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
92 pcix->powbear2 = 0x00000000;
93 pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
94 POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
96 pcix->pitar1 = 0x00000000;
97 pcix->piwbar1 = 0x00000000;
98 pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
99 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
106 pci_set_region(hose->regions + 0,
107 CONFIG_SYS_PCI1_MEM_BUS,
108 CONFIG_SYS_PCI1_MEM_PHYS,
109 CONFIG_SYS_PCI1_MEM_SIZE,
112 pci_set_region(hose->regions + 1,
113 CONFIG_SYS_PCI1_IO_BUS,
114 CONFIG_SYS_PCI1_IO_PHYS,
115 CONFIG_SYS_PCI1_IO_SIZE,
118 hose->region_count = 2;
120 pci_register_hose(hose);
122 #if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
124 * This is a SW workaround for an apparent HW problem
125 * in the PCI controller on the MPC85555/41 CDS boards.
126 * The first config cycle must be to a valid, known
127 * device on the PCI bus in order to trick the PCI
128 * controller state machine into a known valid state.
129 * Without this, the first config cycle has the chance
130 * of hanging the controller permanently, just leaving
131 * it in a semi-working state, or leaving it working.
133 * Pick on the Tundra, Device 17, to get it right.
138 pci_hose_read_config_byte(hose,
139 PCI_BDF(0,BRIDGE_ID,0),
145 hose->last_busno = pci_hose_scan(hose);
147 #ifdef CONFIG_MPC85XX_PCI2
150 hose->first_busno = pci_hose[0].last_busno + 1;
151 hose->last_busno = 0xff;
153 pci_setup_indirect(hose,
154 (CONFIG_SYS_IMMR+0x9000),
155 (CONFIG_SYS_IMMR+0x9004));
157 dev = PCI_BDF(hose->first_busno, 0, 0);
158 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
159 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
160 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
163 * Clear non-reserved bits in status register.
165 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
167 pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
168 pcix2->potear1 = 0x00000000;
169 pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
170 pcix2->powbear1 = 0x00000000;
171 pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
172 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
174 pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
175 pcix2->potear2 = 0x00000000;
176 pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
177 pcix2->powbear2 = 0x00000000;
178 pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
179 POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
181 pcix2->pitar1 = 0x00000000;
182 pcix2->piwbar1 = 0x00000000;
183 pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
184 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
191 pci_set_region(hose->regions + 0,
192 CONFIG_SYS_PCI2_MEM_BUS,
193 CONFIG_SYS_PCI2_MEM_PHYS,
194 CONFIG_SYS_PCI2_MEM_SIZE,
197 pci_set_region(hose->regions + 1,
198 CONFIG_SYS_PCI2_IO_BUS,
199 CONFIG_SYS_PCI2_IO_PHYS,
200 CONFIG_SYS_PCI2_IO_SIZE,
203 hose->region_count = 2;
208 pci_register_hose(hose);
210 hose->last_busno = pci_hose_scan(hose);
213 #endif /* !CONFIG_FSL_PCI_INIT */