2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Roy Zang <tie-fei.zang@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/immap_85xx.h>
12 #include <asm/fsl_serdes.h>
14 #define SRDS1_MAX_LANES 4
16 static u32 serdes1_prtcl_map;
18 static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19 [0x00] = {PCIE1, PCIE2, NONE, NONE},
20 [0x01] = {PCIE1, PCIE2, PCIE3, NONE},
21 [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2},
22 [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2},
25 int is_serdes_configured(enum srds_prtcl device)
27 int ret = (1 << device) & serdes1_prtcl_map;
31 void fsl_serdes_init(void)
33 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
34 u32 pordevsr = in_be32(&gur->pordevsr);
35 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
36 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
39 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
41 if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
42 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
45 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
46 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
47 serdes1_prtcl_map |= (1 << lane_prtcl);