1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
10 #include <asm/processor.h>
16 #include <asm/fsl_law.h>
17 #include <fsl_ddr_sdram.h>
18 #include <linux/delay.h>
21 DECLARE_GLOBAL_DATA_PTR;
22 u32 fsl_ddr_get_intl3r(void);
24 extern u32 __spin_table[];
28 return mfspr(SPRN_PIR);
32 * Determine if U-Boot should keep secondary cores in reset, or let them out
33 * of reset and hold them in a spinloop
35 int hold_cores_in_reset(int verbose)
37 /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
38 if (env_get_yesno("mp_holdoff") == 1) {
40 puts("Secondary cores are being held in reset.\n");
41 puts("See 'mp_holdoff' environment variable\n");
52 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
53 out_be32(&pic->pir, 1 << nr);
54 /* the dummy read works around an errata on early 85xx MP PICs */
55 (void)in_be32(&pic->pir);
56 out_be32(&pic->pir, 0x0);
61 int cpu_status(u32 nr)
63 u32 *table, id = get_my_id();
65 if (hold_cores_in_reset(1))
69 table = (u32 *)&__spin_table;
70 printf("table base @ 0x%p\n", table);
71 } else if (is_core_disabled(nr)) {
74 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
75 printf("Running on cpu %d\n", id);
77 printf("table @ 0x%p\n", table);
78 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
79 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
80 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
86 #ifdef CONFIG_FSL_CORENET
87 int cpu_disable(u32 nr)
89 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
91 setbits_be32(&gur->coredisrl, 1 << nr);
96 int is_core_disabled(int nr) {
97 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
98 u32 coredisrl = in_be32(&gur->coredisrl);
100 return (coredisrl & (1 << nr));
103 int cpu_disable(u32 nr)
105 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
109 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
112 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
115 printf("Invalid cpu number for disable %d\n", nr);
122 int is_core_disabled(int nr) {
123 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
124 u32 devdisr = in_be32(&gur->devdisr);
128 return (devdisr & MPC85xx_DEVDISR_CPU0);
130 return (devdisr & MPC85xx_DEVDISR_CPU1);
132 printf("Invalid cpu number for disable %d\n", nr);
139 static u8 boot_entry_map[4] = {
145 int cpu_release(u32 nr, int argc, char *const argv[])
147 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
150 if (hold_cores_in_reset(1))
153 if (nr == get_my_id()) {
154 printf("Invalid to release the boot core.\n\n");
159 printf("Invalid number of arguments to release.\n\n");
163 boot_addr = simple_strtoull(argv[0], NULL, 16);
166 for (i = 1; i < 3; i++) {
167 if (argv[i][0] != '-') {
168 u8 entry = boot_entry_map[i];
169 val = simple_strtoul(argv[i], NULL, 16);
174 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
176 /* ensure all table updates complete before final address write */
179 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
184 u32 determine_mp_bootpg(unsigned int *pagesize)
187 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
189 u32 granule_size, check;
194 /* use last 4K of mapped memory */
195 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
196 CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
197 CONFIG_SYS_SDRAM_BASE - 4096;
201 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
203 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
204 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
205 * the way boot page chosen in u-boot avoids hitting this erratum. So only
206 * thw workaround for 3-way interleaving is needed.
208 * To make sure boot page translation works with 3-Way DDR interleaving
209 * enforce a check for the following constrains
210 * 8K granule size requires BRSIZE=8K and
211 * bootpg >> log2(BRSIZE) %3 == 1
212 * 4K and 1K granule size requires BRSIZE=4K and
213 * bootpg >> log2(BRSIZE) %3 == 0
215 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
216 e = find_law(bootpg);
218 case LAW_TRGT_IF_DDR_INTLV_123:
219 granule_size = fsl_ddr_get_intl3r() & 0x1f;
220 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
223 bootpg &= 0xffffe000; /* align to 8KB */
224 check = bootpg >> 13;
225 while ((check % 3) != 1)
227 bootpg = check << 13;
228 debug("Boot page (8K) at 0x%08x\n", bootpg);
231 bootpg &= 0xfffff000; /* align to 4KB */
232 check = bootpg >> 12;
233 while ((check % 3) != 0)
235 bootpg = check << 12;
236 debug("Boot page (4K) at 0x%08x\n", bootpg);
243 #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
248 phys_addr_t get_spin_phys_addr(void)
250 return virt_to_phys(&__spin_table);
253 #ifdef CONFIG_FSL_CORENET
254 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
256 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
257 u32 *table = (u32 *)&__spin_table;
258 volatile ccsr_gur_t *gur;
259 volatile ccsr_local_t *ccm;
260 volatile ccsr_rcpm_t *rcpm;
261 volatile ccsr_pic_t *pic;
263 u32 mask = cpu_mask();
266 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
267 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
268 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
269 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
271 whoami = in_be32(&pic->whoami);
272 cpu_up_mask = 1 << whoami;
273 out_be32(&ccm->bstrl, bootpg);
275 e = find_law(bootpg);
276 /* pagesize is only 4K or 8K */
277 if (pagesize == 8192)
278 brsize = LAW_SIZE_8K;
279 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
280 debug("BRSIZE is 0x%x\n", brsize);
282 /* readback to sync write */
283 in_be32(&ccm->bstrar);
285 /* disable time base at the platform */
286 out_be32(&rcpm->ctbenrl, cpu_up_mask);
288 out_be32(&gur->brrl, mask);
290 /* wait for everyone */
292 unsigned int i, cpu, nr_cpus = cpu_numcores();
294 for_each_cpu(i, cpu, nr_cpus, mask) {
295 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
296 cpu_up_mask |= (1 << cpu);
299 if ((cpu_up_mask & mask) == mask)
307 printf("CPU up timeout. CPU up mask is %x should be %x\n",
310 /* enable time base at the platform */
311 out_be32(&rcpm->ctbenrl, 0);
313 /* readback to sync write */
314 in_be32(&rcpm->ctbenrl);
319 out_be32(&rcpm->ctbenrl, mask);
321 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
323 * Disabling Boot Page Translation allows the memory region 0xfffff000
324 * to 0xffffffff to be used normally. Leaving Boot Page Translation
325 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
326 * unusable for normal operation but it does allow OSes to easily
327 * reset a processor core to put it back into U-Boot's spinloop.
329 clrbits_be32(&ccm->bstrar, LAW_EN);
333 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
335 u32 up, cpu_up_mask, whoami;
336 u32 *table = (u32 *)&__spin_table;
338 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
339 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
340 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
344 whoami = in_be32(&pic->whoami);
345 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
347 /* disable time base at the platform */
348 devdisr = in_be32(&gur->devdisr);
350 devdisr |= MPC85xx_DEVDISR_TB0;
352 devdisr |= MPC85xx_DEVDISR_TB1;
353 out_be32(&gur->devdisr, devdisr);
355 /* release the hounds */
356 up = ((1 << cpu_numcores()) - 1);
357 bpcr = in_be32(&ecm->eebpcr);
359 out_be32(&ecm->eebpcr, bpcr);
360 asm("sync; isync; msync");
362 cpu_up_mask = 1 << whoami;
363 /* wait for everyone */
366 for (i = 0; i < cpu_numcores(); i++) {
367 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
368 cpu_up_mask |= (1 << i);
371 if ((cpu_up_mask & up) == up)
379 printf("CPU up timeout. CPU up mask is %x should be %x\n",
382 /* enable time base at the platform */
384 devdisr |= MPC85xx_DEVDISR_TB1;
386 devdisr |= MPC85xx_DEVDISR_TB0;
387 out_be32(&gur->devdisr, devdisr);
389 /* readback to sync write */
390 in_be32(&gur->devdisr);
395 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
396 out_be32(&gur->devdisr, devdisr);
398 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
400 * Disabling Boot Page Translation allows the memory region 0xfffff000
401 * to 0xffffffff to be used normally. Leaving Boot Page Translation
402 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
403 * unusable for normal operation but it does allow OSes to easily
404 * reset a processor core to put it back into U-Boot's spinloop.
406 clrbits_be32(&ecm->bptr, 0x80000000);
411 void cpu_mp_lmb_reserve(struct lmb *lmb)
413 u32 bootpg = determine_mp_bootpg(NULL);
415 lmb_reserve(lmb, bootpg, 4096);
420 extern u32 __secondary_start_page;
421 extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
424 ulong fixup = (u32)&__secondary_start_page;
425 u32 bootpg, bootpg_map, pagesize;
427 bootpg = determine_mp_bootpg(&pagesize);
430 * pagesize is only 4K or 8K
431 * we only use the last 4K of boot page
432 * bootpg_map saves the address for the boot page
433 * 8K is used for the workaround of 3-way DDR interleaving
438 if (pagesize == 8192)
439 bootpg += 4096; /* use 2nd half */
441 /* Some OSes expect secondary cores to be held in reset */
442 if (hold_cores_in_reset(0))
446 * Store the bootpg's cache-able half address for use by secondary
447 * CPU cores to continue to boot
449 __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
451 /* Store spin table's physical address for use by secondary cores */
452 __spin_table_addr = (u32)get_spin_phys_addr();
454 /* flush bootpg it before copying invalidate any staled cacheline */
455 flush_cache(bootpg, 4096);
457 /* look for the tlb covering the reset page, there better be one */
458 i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
460 /* we found a match */
462 /* map reset page to bootpg so we can copy code there */
465 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
466 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
467 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
469 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
471 plat_mp_up(bootpg_map, pagesize);
473 puts("WARNING: No reset page TLB. "
474 "Skipping secondary core setup\n");