2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/processor.h>
13 #include <asm/fsl_law.h>
14 #include <asm/fsl_ddr_sdram.h>
17 DECLARE_GLOBAL_DATA_PTR;
18 u32 fsl_ddr_get_intl3r(void);
20 extern u32 __spin_table[];
24 return mfspr(SPRN_PIR);
28 * Determine if U-Boot should keep secondary cores in reset, or let them out
29 * of reset and hold them in a spinloop
31 int hold_cores_in_reset(int verbose)
33 /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
34 if (getenv_yesno("mp_holdoff") == 1) {
36 puts("Secondary cores are being held in reset.\n");
37 puts("See 'mp_holdoff' environment variable\n");
48 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
49 out_be32(&pic->pir, 1 << nr);
50 /* the dummy read works around an errata on early 85xx MP PICs */
51 (void)in_be32(&pic->pir);
52 out_be32(&pic->pir, 0x0);
57 int cpu_status(int nr)
59 u32 *table, id = get_my_id();
61 if (hold_cores_in_reset(1))
65 table = (u32 *)&__spin_table;
66 printf("table base @ 0x%p\n", table);
67 } else if (is_core_disabled(nr)) {
70 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
71 printf("Running on cpu %d\n", id);
73 printf("table @ 0x%p\n", table);
74 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
75 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
76 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
82 #ifdef CONFIG_FSL_CORENET
83 int cpu_disable(int nr)
85 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
87 setbits_be32(&gur->coredisrl, 1 << nr);
92 int is_core_disabled(int nr) {
93 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
94 u32 coredisrl = in_be32(&gur->coredisrl);
96 return (coredisrl & (1 << nr));
99 int cpu_disable(int nr)
101 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
105 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
108 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
111 printf("Invalid cpu number for disable %d\n", nr);
118 int is_core_disabled(int nr) {
119 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
120 u32 devdisr = in_be32(&gur->devdisr);
124 return (devdisr & MPC85xx_DEVDISR_CPU0);
126 return (devdisr & MPC85xx_DEVDISR_CPU1);
128 printf("Invalid cpu number for disable %d\n", nr);
135 static u8 boot_entry_map[4] = {
141 int cpu_release(int nr, int argc, char * const argv[])
143 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
146 if (hold_cores_in_reset(1))
149 if (nr == get_my_id()) {
150 printf("Invalid to release the boot core.\n\n");
155 printf("Invalid number of arguments to release.\n\n");
159 boot_addr = simple_strtoull(argv[0], NULL, 16);
162 for (i = 1; i < 3; i++) {
163 if (argv[i][0] != '-') {
164 u8 entry = boot_entry_map[i];
165 val = simple_strtoul(argv[i], NULL, 16);
170 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
172 /* ensure all table updates complete before final address write */
175 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
180 u32 determine_mp_bootpg(unsigned int *pagesize)
183 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
185 u32 granule_size, check;
190 /* use last 4K of mapped memory */
191 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
192 CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
193 CONFIG_SYS_SDRAM_BASE - 4096;
197 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
199 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
200 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
201 * the way boot page chosen in u-boot avoids hitting this erratum. So only
202 * thw workaround for 3-way interleaving is needed.
204 * To make sure boot page translation works with 3-Way DDR interleaving
205 * enforce a check for the following constrains
206 * 8K granule size requires BRSIZE=8K and
207 * bootpg >> log2(BRSIZE) %3 == 1
208 * 4K and 1K granule size requires BRSIZE=4K and
209 * bootpg >> log2(BRSIZE) %3 == 0
211 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
212 e = find_law(bootpg);
214 case LAW_TRGT_IF_DDR_INTLV_123:
215 granule_size = fsl_ddr_get_intl3r() & 0x1f;
216 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
219 bootpg &= 0xffffe000; /* align to 8KB */
220 check = bootpg >> 13;
221 while ((check % 3) != 1)
223 bootpg = check << 13;
224 debug("Boot page (8K) at 0x%08x\n", bootpg);
227 bootpg &= 0xfffff000; /* align to 4KB */
228 check = bootpg >> 12;
229 while ((check % 3) != 0)
231 bootpg = check << 12;
232 debug("Boot page (4K) at 0x%08x\n", bootpg);
239 #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
244 phys_addr_t get_spin_phys_addr(void)
246 return virt_to_phys(&__spin_table);
249 #ifdef CONFIG_FSL_CORENET
250 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
252 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
253 u32 *table = (u32 *)&__spin_table;
254 volatile ccsr_gur_t *gur;
255 volatile ccsr_local_t *ccm;
256 volatile ccsr_rcpm_t *rcpm;
257 volatile ccsr_pic_t *pic;
259 u32 mask = cpu_mask();
262 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
263 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
264 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
265 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
267 whoami = in_be32(&pic->whoami);
268 cpu_up_mask = 1 << whoami;
269 out_be32(&ccm->bstrl, bootpg);
271 e = find_law(bootpg);
272 /* pagesize is only 4K or 8K */
273 if (pagesize == 8192)
274 brsize = LAW_SIZE_8K;
275 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
276 debug("BRSIZE is 0x%x\n", brsize);
278 /* readback to sync write */
279 in_be32(&ccm->bstrar);
281 /* disable time base at the platform */
282 out_be32(&rcpm->ctbenrl, cpu_up_mask);
284 out_be32(&gur->brrl, mask);
286 /* wait for everyone */
288 unsigned int i, cpu, nr_cpus = cpu_numcores();
290 for_each_cpu(i, cpu, nr_cpus, mask) {
291 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
292 cpu_up_mask |= (1 << cpu);
295 if ((cpu_up_mask & mask) == mask)
303 printf("CPU up timeout. CPU up mask is %x should be %x\n",
306 /* enable time base at the platform */
307 out_be32(&rcpm->ctbenrl, 0);
309 /* readback to sync write */
310 in_be32(&rcpm->ctbenrl);
315 out_be32(&rcpm->ctbenrl, mask);
317 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
319 * Disabling Boot Page Translation allows the memory region 0xfffff000
320 * to 0xffffffff to be used normally. Leaving Boot Page Translation
321 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
322 * unusable for normal operation but it does allow OSes to easily
323 * reset a processor core to put it back into U-Boot's spinloop.
325 clrbits_be32(&ccm->bstrar, LAW_EN);
329 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
331 u32 up, cpu_up_mask, whoami;
332 u32 *table = (u32 *)&__spin_table;
334 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
335 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
336 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
340 whoami = in_be32(&pic->whoami);
341 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
343 /* disable time base at the platform */
344 devdisr = in_be32(&gur->devdisr);
346 devdisr |= MPC85xx_DEVDISR_TB0;
348 devdisr |= MPC85xx_DEVDISR_TB1;
349 out_be32(&gur->devdisr, devdisr);
351 /* release the hounds */
352 up = ((1 << cpu_numcores()) - 1);
353 bpcr = in_be32(&ecm->eebpcr);
355 out_be32(&ecm->eebpcr, bpcr);
356 asm("sync; isync; msync");
358 cpu_up_mask = 1 << whoami;
359 /* wait for everyone */
362 for (i = 0; i < cpu_numcores(); i++) {
363 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
364 cpu_up_mask |= (1 << i);
367 if ((cpu_up_mask & up) == up)
375 printf("CPU up timeout. CPU up mask is %x should be %x\n",
378 /* enable time base at the platform */
380 devdisr |= MPC85xx_DEVDISR_TB1;
382 devdisr |= MPC85xx_DEVDISR_TB0;
383 out_be32(&gur->devdisr, devdisr);
385 /* readback to sync write */
386 in_be32(&gur->devdisr);
391 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
392 out_be32(&gur->devdisr, devdisr);
394 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
396 * Disabling Boot Page Translation allows the memory region 0xfffff000
397 * to 0xffffffff to be used normally. Leaving Boot Page Translation
398 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
399 * unusable for normal operation but it does allow OSes to easily
400 * reset a processor core to put it back into U-Boot's spinloop.
402 clrbits_be32(&ecm->bptr, 0x80000000);
407 void cpu_mp_lmb_reserve(struct lmb *lmb)
409 u32 bootpg = determine_mp_bootpg(NULL);
411 lmb_reserve(lmb, bootpg, 4096);
416 extern u32 __secondary_start_page;
417 extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
420 ulong fixup = (u32)&__secondary_start_page;
421 u32 bootpg, bootpg_map, pagesize;
423 bootpg = determine_mp_bootpg(&pagesize);
426 * pagesize is only 4K or 8K
427 * we only use the last 4K of boot page
428 * bootpg_map saves the address for the boot page
429 * 8K is used for the workaround of 3-way DDR interleaving
434 if (pagesize == 8192)
435 bootpg += 4096; /* use 2nd half */
437 /* Some OSes expect secondary cores to be held in reset */
438 if (hold_cores_in_reset(0))
442 * Store the bootpg's cache-able half address for use by secondary
443 * CPU cores to continue to boot
445 __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
447 /* Store spin table's physical address for use by secondary cores */
448 __spin_table_addr = (u32)get_spin_phys_addr();
450 /* flush bootpg it before copying invalidate any staled cacheline */
451 flush_cache(bootpg, 4096);
453 /* look for the tlb covering the reset page, there better be one */
454 i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
456 /* we found a match */
458 /* map reset page to bootpg so we can copy code there */
461 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
462 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
463 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
465 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
467 plat_mp_up(bootpg_map, pagesize);
469 puts("WARNING: No reset page TLB. "
470 "Skipping secondary core setup\n");