1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
7 #include <asm/processor.h>
12 #include <asm/fsl_law.h>
13 #include <fsl_ddr_sdram.h>
16 DECLARE_GLOBAL_DATA_PTR;
17 u32 fsl_ddr_get_intl3r(void);
19 extern u32 __spin_table[];
23 return mfspr(SPRN_PIR);
27 * Determine if U-Boot should keep secondary cores in reset, or let them out
28 * of reset and hold them in a spinloop
30 int hold_cores_in_reset(int verbose)
32 /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
33 if (env_get_yesno("mp_holdoff") == 1) {
35 puts("Secondary cores are being held in reset.\n");
36 puts("See 'mp_holdoff' environment variable\n");
47 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
48 out_be32(&pic->pir, 1 << nr);
49 /* the dummy read works around an errata on early 85xx MP PICs */
50 (void)in_be32(&pic->pir);
51 out_be32(&pic->pir, 0x0);
56 int cpu_status(int nr)
58 u32 *table, id = get_my_id();
60 if (hold_cores_in_reset(1))
64 table = (u32 *)&__spin_table;
65 printf("table base @ 0x%p\n", table);
66 } else if (is_core_disabled(nr)) {
69 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
70 printf("Running on cpu %d\n", id);
72 printf("table @ 0x%p\n", table);
73 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
74 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
75 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
81 #ifdef CONFIG_FSL_CORENET
82 int cpu_disable(int nr)
84 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
86 setbits_be32(&gur->coredisrl, 1 << nr);
91 int is_core_disabled(int nr) {
92 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
93 u32 coredisrl = in_be32(&gur->coredisrl);
95 return (coredisrl & (1 << nr));
98 int cpu_disable(int nr)
100 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
104 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
107 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
110 printf("Invalid cpu number for disable %d\n", nr);
117 int is_core_disabled(int nr) {
118 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
119 u32 devdisr = in_be32(&gur->devdisr);
123 return (devdisr & MPC85xx_DEVDISR_CPU0);
125 return (devdisr & MPC85xx_DEVDISR_CPU1);
127 printf("Invalid cpu number for disable %d\n", nr);
134 static u8 boot_entry_map[4] = {
140 int cpu_release(int nr, int argc, char * const argv[])
142 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
145 if (hold_cores_in_reset(1))
148 if (nr == get_my_id()) {
149 printf("Invalid to release the boot core.\n\n");
154 printf("Invalid number of arguments to release.\n\n");
158 boot_addr = simple_strtoull(argv[0], NULL, 16);
161 for (i = 1; i < 3; i++) {
162 if (argv[i][0] != '-') {
163 u8 entry = boot_entry_map[i];
164 val = simple_strtoul(argv[i], NULL, 16);
169 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
171 /* ensure all table updates complete before final address write */
174 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
179 u32 determine_mp_bootpg(unsigned int *pagesize)
182 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
184 u32 granule_size, check;
189 /* use last 4K of mapped memory */
190 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
191 CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
192 CONFIG_SYS_SDRAM_BASE - 4096;
196 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
198 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
199 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
200 * the way boot page chosen in u-boot avoids hitting this erratum. So only
201 * thw workaround for 3-way interleaving is needed.
203 * To make sure boot page translation works with 3-Way DDR interleaving
204 * enforce a check for the following constrains
205 * 8K granule size requires BRSIZE=8K and
206 * bootpg >> log2(BRSIZE) %3 == 1
207 * 4K and 1K granule size requires BRSIZE=4K and
208 * bootpg >> log2(BRSIZE) %3 == 0
210 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
211 e = find_law(bootpg);
213 case LAW_TRGT_IF_DDR_INTLV_123:
214 granule_size = fsl_ddr_get_intl3r() & 0x1f;
215 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
218 bootpg &= 0xffffe000; /* align to 8KB */
219 check = bootpg >> 13;
220 while ((check % 3) != 1)
222 bootpg = check << 13;
223 debug("Boot page (8K) at 0x%08x\n", bootpg);
226 bootpg &= 0xfffff000; /* align to 4KB */
227 check = bootpg >> 12;
228 while ((check % 3) != 0)
230 bootpg = check << 12;
231 debug("Boot page (4K) at 0x%08x\n", bootpg);
238 #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
243 phys_addr_t get_spin_phys_addr(void)
245 return virt_to_phys(&__spin_table);
248 #ifdef CONFIG_FSL_CORENET
249 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
251 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
252 u32 *table = (u32 *)&__spin_table;
253 volatile ccsr_gur_t *gur;
254 volatile ccsr_local_t *ccm;
255 volatile ccsr_rcpm_t *rcpm;
256 volatile ccsr_pic_t *pic;
258 u32 mask = cpu_mask();
261 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
262 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
263 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
264 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
266 whoami = in_be32(&pic->whoami);
267 cpu_up_mask = 1 << whoami;
268 out_be32(&ccm->bstrl, bootpg);
270 e = find_law(bootpg);
271 /* pagesize is only 4K or 8K */
272 if (pagesize == 8192)
273 brsize = LAW_SIZE_8K;
274 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
275 debug("BRSIZE is 0x%x\n", brsize);
277 /* readback to sync write */
278 in_be32(&ccm->bstrar);
280 /* disable time base at the platform */
281 out_be32(&rcpm->ctbenrl, cpu_up_mask);
283 out_be32(&gur->brrl, mask);
285 /* wait for everyone */
287 unsigned int i, cpu, nr_cpus = cpu_numcores();
289 for_each_cpu(i, cpu, nr_cpus, mask) {
290 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
291 cpu_up_mask |= (1 << cpu);
294 if ((cpu_up_mask & mask) == mask)
302 printf("CPU up timeout. CPU up mask is %x should be %x\n",
305 /* enable time base at the platform */
306 out_be32(&rcpm->ctbenrl, 0);
308 /* readback to sync write */
309 in_be32(&rcpm->ctbenrl);
314 out_be32(&rcpm->ctbenrl, mask);
316 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
318 * Disabling Boot Page Translation allows the memory region 0xfffff000
319 * to 0xffffffff to be used normally. Leaving Boot Page Translation
320 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
321 * unusable for normal operation but it does allow OSes to easily
322 * reset a processor core to put it back into U-Boot's spinloop.
324 clrbits_be32(&ccm->bstrar, LAW_EN);
328 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
330 u32 up, cpu_up_mask, whoami;
331 u32 *table = (u32 *)&__spin_table;
333 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
334 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
335 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
339 whoami = in_be32(&pic->whoami);
340 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
342 /* disable time base at the platform */
343 devdisr = in_be32(&gur->devdisr);
345 devdisr |= MPC85xx_DEVDISR_TB0;
347 devdisr |= MPC85xx_DEVDISR_TB1;
348 out_be32(&gur->devdisr, devdisr);
350 /* release the hounds */
351 up = ((1 << cpu_numcores()) - 1);
352 bpcr = in_be32(&ecm->eebpcr);
354 out_be32(&ecm->eebpcr, bpcr);
355 asm("sync; isync; msync");
357 cpu_up_mask = 1 << whoami;
358 /* wait for everyone */
361 for (i = 0; i < cpu_numcores(); i++) {
362 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
363 cpu_up_mask |= (1 << i);
366 if ((cpu_up_mask & up) == up)
374 printf("CPU up timeout. CPU up mask is %x should be %x\n",
377 /* enable time base at the platform */
379 devdisr |= MPC85xx_DEVDISR_TB1;
381 devdisr |= MPC85xx_DEVDISR_TB0;
382 out_be32(&gur->devdisr, devdisr);
384 /* readback to sync write */
385 in_be32(&gur->devdisr);
390 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
391 out_be32(&gur->devdisr, devdisr);
393 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
395 * Disabling Boot Page Translation allows the memory region 0xfffff000
396 * to 0xffffffff to be used normally. Leaving Boot Page Translation
397 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
398 * unusable for normal operation but it does allow OSes to easily
399 * reset a processor core to put it back into U-Boot's spinloop.
401 clrbits_be32(&ecm->bptr, 0x80000000);
406 void cpu_mp_lmb_reserve(struct lmb *lmb)
408 u32 bootpg = determine_mp_bootpg(NULL);
410 lmb_reserve(lmb, bootpg, 4096);
415 extern u32 __secondary_start_page;
416 extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
419 ulong fixup = (u32)&__secondary_start_page;
420 u32 bootpg, bootpg_map, pagesize;
422 bootpg = determine_mp_bootpg(&pagesize);
425 * pagesize is only 4K or 8K
426 * we only use the last 4K of boot page
427 * bootpg_map saves the address for the boot page
428 * 8K is used for the workaround of 3-way DDR interleaving
433 if (pagesize == 8192)
434 bootpg += 4096; /* use 2nd half */
436 /* Some OSes expect secondary cores to be held in reset */
437 if (hold_cores_in_reset(0))
441 * Store the bootpg's cache-able half address for use by secondary
442 * CPU cores to continue to boot
444 __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
446 /* Store spin table's physical address for use by secondary cores */
447 __spin_table_addr = (u32)get_spin_phys_addr();
449 /* flush bootpg it before copying invalidate any staled cacheline */
450 flush_cache(bootpg, 4096);
452 /* look for the tlb covering the reset page, there better be one */
453 i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
455 /* we found a match */
457 /* map reset page to bootpg so we can copy code there */
460 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
461 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
462 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
464 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
466 plat_mp_up(bootpg_map, pagesize);
468 puts("WARNING: No reset page TLB. "
469 "Skipping secondary core setup\n");