2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
30 #include <linux/ctype.h>
32 #ifdef CONFIG_FSL_ESDHC
33 #include <fsl_esdhc.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 extern void ft_qe_setup(void *blob);
39 extern void ft_fixup_num_cores(void *blob);
44 void ft_fixup_cpu(void *blob, u64 memory_limit)
47 ulong spin_tbl_addr = get_spin_phys_addr();
48 u32 bootpg = determine_mp_bootpg();
51 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
52 while (off != -FDT_ERR_NOTFOUND) {
53 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
57 fdt_setprop_string(blob, off, "status", "okay");
59 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
60 val = cpu_to_fdt32(val);
61 fdt_setprop_string(blob, off, "status",
63 fdt_setprop_string(blob, off, "enable-method",
65 fdt_setprop(blob, off, "cpu-release-addr",
69 printf ("cpu NULL\n");
71 off = fdt_node_offset_by_prop_value(blob, off,
72 "device_type", "cpu", 4);
75 /* Reserve the boot page so OSes dont use it */
76 if ((u64)bootpg < memory_limit) {
77 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
79 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
84 #ifdef CONFIG_SYS_FSL_CPC
85 static inline void ft_fixup_l3cache(void *blob, int off)
87 u32 line_size, num_ways, size, num_sets;
88 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
89 u32 cfg0 = in_be32(&cpc->cpccfg0);
91 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
92 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
93 line_size = CPC_CFG0_LINE_SZ(cfg0);
94 num_sets = size / (line_size * num_ways);
96 fdt_setprop(blob, off, "cache-unified", NULL, 0);
97 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
98 fdt_setprop_cell(blob, off, "cache-size", size);
99 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
100 fdt_setprop_cell(blob, off, "cache-level", 3);
101 #ifdef CONFIG_SYS_CACHE_STASHING
102 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
106 #define ft_fixup_l3cache(x, y)
109 #if defined(CONFIG_L2_CACHE)
110 /* return size in kilobytes */
111 static inline u32 l2cache_size(void)
113 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
114 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
115 u32 ver = SVR_SOC_VER(get_svr());
117 switch (l2siz_field) {
121 if (ver == SVR_8540 || ver == SVR_8560 ||
122 ver == SVR_8541 || ver == SVR_8541_E ||
123 ver == SVR_8555 || ver == SVR_8555_E)
129 if (ver == SVR_8540 || ver == SVR_8560 ||
130 ver == SVR_8541 || ver == SVR_8541_E ||
131 ver == SVR_8555 || ver == SVR_8555_E)
144 static inline void ft_fixup_l2cache(void *blob)
148 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
151 const u32 line_size = 32;
152 const u32 num_ways = 8;
153 const u32 size = l2cache_size() * 1024;
154 const u32 num_sets = size / (line_size * num_ways);
156 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
158 debug("no cpu node fount\n");
162 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
165 debug("no next-level-cache property\n");
169 off = fdt_node_offset_by_phandle(blob, *ph);
171 printf("%s: %s\n", __func__, fdt_strerror(off));
176 if (isdigit(cpu->name[0]))
177 len = sprintf(compat_buf,
178 "fsl,mpc%s-l2-cache-controller", cpu->name);
180 len = sprintf(compat_buf,
181 "fsl,%c%s-l2-cache-controller",
182 tolower(cpu->name[0]), cpu->name + 1);
184 sprintf(&compat_buf[len + 1], "cache");
186 fdt_setprop(blob, off, "cache-unified", NULL, 0);
187 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
188 fdt_setprop_cell(blob, off, "cache-size", size);
189 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
190 fdt_setprop_cell(blob, off, "cache-level", 2);
191 fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
193 /* we dont bother w/L3 since no platform of this type has one */
195 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
196 static inline void ft_fixup_l2cache(void *blob)
198 int off, l2_off, l3_off = -1;
200 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
201 u32 size, line_size, num_ways, num_sets;
203 size = (l2cfg0 & 0x3fff) * 64 * 1024;
204 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
205 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
206 num_sets = size / (line_size * num_ways);
208 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
210 while (off != -FDT_ERR_NOTFOUND) {
211 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
214 debug("no next-level-cache property\n");
218 l2_off = fdt_node_offset_by_phandle(blob, *ph);
220 printf("%s: %s\n", __func__, fdt_strerror(off));
224 #ifdef CONFIG_SYS_CACHE_STASHING
226 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
228 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
229 (*reg * 2) + 32 + 1);
233 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
234 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
235 fdt_setprop_cell(blob, l2_off, "cache-size", size);
236 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
237 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
238 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
241 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
244 debug("no next-level-cache property\n");
250 off = fdt_node_offset_by_prop_value(blob, off,
251 "device_type", "cpu", 4);
254 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
256 printf("%s: %s\n", __func__, fdt_strerror(off));
259 ft_fixup_l3cache(blob, l3_off);
263 #define ft_fixup_l2cache(x)
266 static inline void ft_fixup_cache(void *blob)
270 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
272 while (off != -FDT_ERR_NOTFOUND) {
273 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
274 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
275 u32 isize, iline_size, inum_sets, inum_ways;
276 u32 dsize, dline_size, dnum_sets, dnum_ways;
279 dsize = (l1cfg0 & 0x7ff) * 1024;
280 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
281 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
282 dnum_sets = dsize / (dline_size * dnum_ways);
284 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
285 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
286 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
288 #ifdef CONFIG_SYS_CACHE_STASHING
290 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
292 fdt_setprop_cell(blob, off, "cache-stash-id",
293 (*reg * 2) + 32 + 0);
298 isize = (l1cfg1 & 0x7ff) * 1024;
299 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
300 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
301 inum_sets = isize / (iline_size * inum_ways);
303 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
304 fdt_setprop_cell(blob, off, "i-cache-size", isize);
305 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
307 off = fdt_node_offset_by_prop_value(blob, off,
308 "device_type", "cpu", 4);
311 ft_fixup_l2cache(blob);
315 void fdt_add_enet_stashing(void *fdt)
317 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
319 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
321 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
324 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
325 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
328 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
329 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
332 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
334 printf("WARNING enable to set clock-frequency "
335 "for %s: %s\n", compat, fdt_strerror(off));
339 static void ft_fixup_dpaa_clks(void *blob)
343 get_sys_info(&sysinfo);
344 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
345 sysinfo.freqFMan[0]);
347 #if (CONFIG_SYS_NUM_FMAN == 2)
348 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
349 sysinfo.freqFMan[1]);
352 #ifdef CONFIG_SYS_DPAA_PME
353 do_fixup_by_compat_u32(blob, "fsl,pme",
354 "clock-frequency", sysinfo.freqPME, 1);
358 #define ft_fixup_dpaa_clks(x)
362 static void ft_fixup_qe_snum(void *blob)
366 svr = mfspr(SPRN_SVR);
367 if (SVR_SOC_VER(svr) == SVR_8569_E) {
368 if(IS_SVR_REV(svr, 1, 0))
369 do_fixup_by_compat_u32(blob, "fsl,qe",
370 "fsl,qe-num-snums", 46, 1);
372 do_fixup_by_compat_u32(blob, "fsl,qe",
373 "fsl,qe-num-snums", 76, 1);
378 void ft_cpu_setup(void *blob, bd_t *bd)
384 /* delete crypto node if not on an E-processor */
385 if (!IS_E_PROCESSOR(get_svr()))
386 fdt_fixup_crypto_node(blob, 0);
388 fdt_fixup_ethernet(blob);
390 fdt_add_enet_stashing(blob);
392 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
393 "timebase-frequency", get_tbclk(), 1);
394 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
395 "bus-frequency", bd->bi_busfreq, 1);
396 get_sys_info(&sysinfo);
397 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
398 while (off != -FDT_ERR_NOTFOUND) {
399 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
400 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
401 fdt_setprop(blob, off, "clock-frequency", &val, 4);
402 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
405 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
406 "bus-frequency", bd->bi_busfreq, 1);
408 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
409 "bus-frequency", gd->lbc_clk, 1);
410 do_fixup_by_compat_u32(blob, "fsl,elbc",
411 "bus-frequency", gd->lbc_clk, 1);
414 ft_fixup_qe_snum(blob);
417 #ifdef CONFIG_SYS_NS16550
418 do_fixup_by_compat_u32(blob, "ns16550",
419 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
423 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
424 "current-speed", bd->bi_baudrate, 1);
426 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
427 "clock-frequency", bd->bi_brgfreq, 1);
430 #ifdef CONFIG_FSL_CORENET
431 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
432 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
435 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
438 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
439 ft_fixup_num_cores(blob);
442 ft_fixup_cache(blob);
444 #if defined(CONFIG_FSL_ESDHC)
445 fdt_fixup_esdhc(blob, bd);
448 ft_fixup_dpaa_clks(blob);