1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 #include <clock_legacy.h>
13 #include <linux/libfdt.h>
14 #include <fdt_support.h>
15 #include <asm/processor.h>
16 #include <linux/ctype.h>
18 #include <asm/fsl_fdt.h>
19 #include <asm/fsl_portals.h>
20 #include <fsl_qbman.h>
22 #ifdef CONFIG_FSL_ESDHC
23 #include <fsl_esdhc.h>
25 #ifdef CONFIG_SYS_DPAA_FMAN
29 DECLARE_GLOBAL_DATA_PTR;
31 extern void ft_qe_setup(void *blob);
32 extern void ft_fixup_num_cores(void *blob);
33 extern void ft_srio_setup(void *blob);
38 void ft_fixup_cpu(void *blob, u64 memory_limit)
41 phys_addr_t spin_tbl_addr = get_spin_phys_addr();
42 u32 bootpg = determine_mp_bootpg(NULL);
44 const char *enable_method;
45 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
47 int tdm_hwconfig_enabled = 0;
48 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
51 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
52 while (off != -FDT_ERR_NOTFOUND) {
53 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
56 u32 phys_cpu_id = thread_to_core(*reg);
57 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
58 val = cpu_to_fdt64(val);
60 fdt_setprop_string(blob, off, "status",
63 fdt_setprop_string(blob, off, "status",
67 if (hold_cores_in_reset(0)) {
68 #ifdef CONFIG_FSL_CORENET
69 /* Cores held in reset, use BRR to release */
70 enable_method = "fsl,brr-holdoff";
72 /* Cores held in reset, use EEBPCR to release */
73 enable_method = "fsl,eebpcr-holdoff";
76 /* Cores out of reset and in a spin-loop */
77 enable_method = "spin-table";
79 fdt_setprop(blob, off, "cpu-release-addr",
83 fdt_setprop_string(blob, off, "enable-method",
86 printf ("cpu NULL\n");
88 off = fdt_node_offset_by_prop_value(blob, off,
89 "device_type", "cpu", 4);
92 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
93 #define CONFIG_MEM_HOLE_16M 0x1000000
95 * Extract hwconfig from environment.
96 * Search for tdm entry in hwconfig.
98 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
100 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
102 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
103 if (tdm_hwconfig_enabled) {
104 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
105 CONFIG_MEM_HOLE_16M);
107 printf("Failed to reserve memory for tdm: %s\n",
112 /* Reserve the boot page so OSes dont use it */
113 if ((u64)bootpg < memory_limit) {
114 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
116 printf("Failed to reserve memory for bootpg: %s\n",
120 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
122 * Reserve the default boot page so OSes dont use it.
123 * The default boot page is always mapped to bootpg above using
124 * boot page translation.
126 if (0xfffff000ull < memory_limit) {
127 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
129 printf("Failed to reserve memory for 0xfffff000: %s\n",
135 /* Reserve spin table page */
136 if (spin_tbl_addr < memory_limit) {
137 off = fdt_add_mem_rsv(blob,
138 (spin_tbl_addr & ~0xffful), 4096);
140 printf("Failed to reserve memory for spin table: %s\n",
143 #ifdef CONFIG_DEEP_SLEEP
144 #ifdef CONFIG_SPL_MMC_BOOT
145 off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
146 CONFIG_SYS_MMC_U_BOOT_SIZE);
148 printf("Failed to reserve memory for SD deep sleep: %s\n",
150 #elif defined(CONFIG_SPL_SPI_BOOT)
151 off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
152 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
154 printf("Failed to reserve memory for SPI deep sleep: %s\n",
161 #ifdef CONFIG_SYS_FSL_CPC
162 static inline void ft_fixup_l3cache(void *blob, int off)
164 u32 line_size, num_ways, size, num_sets;
165 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
166 u32 cfg0 = in_be32(&cpc->cpccfg0);
168 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
169 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
170 line_size = CPC_CFG0_LINE_SZ(cfg0);
171 num_sets = size / (line_size * num_ways);
173 fdt_setprop(blob, off, "cache-unified", NULL, 0);
174 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
175 fdt_setprop_cell(blob, off, "cache-size", size);
176 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
177 fdt_setprop_cell(blob, off, "cache-level", 3);
178 #ifdef CONFIG_SYS_CACHE_STASHING
179 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
183 #define ft_fixup_l3cache(x, y)
186 #if defined(CONFIG_L2_CACHE) || \
187 defined(CONFIG_BACKSIDE_L2_CACHE) || \
188 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
189 static inline void ft_fixup_l2cache_compatible(void *blob, int off)
192 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
197 if (isdigit(cpu->name[0])) {
198 /* MPCxxxx, where xxxx == 4-digit number */
199 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
202 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
203 len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
204 tolower(cpu->name[0]), cpu->name + 1) + 1;
208 * append "cache" after the NULL character that the previous
209 * sprintf wrote. This is how a device tree stores multiple
210 * strings in a property.
212 len += sprintf(buf + len, "cache") + 1;
214 fdt_setprop(blob, off, "compatible", buf, len);
219 #if defined(CONFIG_L2_CACHE)
220 /* return size in kilobytes */
221 static inline u32 l2cache_size(void)
223 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
224 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
225 u32 ver = SVR_SOC_VER(get_svr());
227 switch (l2siz_field) {
231 if (ver == SVR_8540 || ver == SVR_8560 ||
232 ver == SVR_8541 || ver == SVR_8555)
238 if (ver == SVR_8540 || ver == SVR_8560 ||
239 ver == SVR_8541 || ver == SVR_8555)
252 static inline void ft_fixup_l2cache(void *blob)
257 const u32 line_size = 32;
258 const u32 num_ways = 8;
259 const u32 size = l2cache_size() * 1024;
260 const u32 num_sets = size / (line_size * num_ways);
262 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
264 debug("no cpu node fount\n");
268 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
271 debug("no next-level-cache property\n");
275 off = fdt_node_offset_by_phandle(blob, *ph);
277 printf("%s: %s\n", __func__, fdt_strerror(off));
281 ft_fixup_l2cache_compatible(blob, off);
282 fdt_setprop(blob, off, "cache-unified", NULL, 0);
283 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
284 fdt_setprop_cell(blob, off, "cache-size", size);
285 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
286 fdt_setprop_cell(blob, off, "cache-level", 2);
288 /* we dont bother w/L3 since no platform of this type has one */
290 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
291 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
292 static inline void ft_fixup_l2cache(void *blob)
294 int off, l2_off, l3_off = -1;
296 #ifdef CONFIG_BACKSIDE_L2_CACHE
297 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
299 struct ccsr_cluster_l2 *l2cache =
300 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
301 u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
303 u32 size, line_size, num_ways, num_sets;
306 /* P2040/P2040E has no L2, so dont set any L2 props */
307 if (SVR_SOC_VER(get_svr()) == SVR_P2040)
310 size = (l2cfg0 & 0x3fff) * 64 * 1024;
311 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
312 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
313 num_sets = size / (line_size * num_ways);
315 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
317 while (off != -FDT_ERR_NOTFOUND) {
318 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
321 debug("no next-level-cache property\n");
325 l2_off = fdt_node_offset_by_phandle(blob, *ph);
327 printf("%s: %s\n", __func__, fdt_strerror(off));
332 #ifdef CONFIG_SYS_CACHE_STASHING
333 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
334 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
335 /* Only initialize every eighth thread */
336 if (reg && !((*reg) % 8)) {
337 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
338 (*reg / 4) + 32 + 1);
342 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
343 (*reg * 2) + 32 + 1);
348 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
349 fdt_setprop_cell(blob, l2_off, "cache-block-size",
351 fdt_setprop_cell(blob, l2_off, "cache-size", size);
352 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
353 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
354 ft_fixup_l2cache_compatible(blob, l2_off);
358 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
361 debug("no next-level-cache property\n");
367 off = fdt_node_offset_by_prop_value(blob, off,
368 "device_type", "cpu", 4);
371 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
373 printf("%s: %s\n", __func__, fdt_strerror(off));
376 ft_fixup_l3cache(blob, l3_off);
380 #define ft_fixup_l2cache(x)
383 static inline void ft_fixup_cache(void *blob)
387 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
389 while (off != -FDT_ERR_NOTFOUND) {
390 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
391 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
392 u32 isize, iline_size, inum_sets, inum_ways;
393 u32 dsize, dline_size, dnum_sets, dnum_ways;
396 dsize = (l1cfg0 & 0x7ff) * 1024;
397 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
398 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
399 dnum_sets = dsize / (dline_size * dnum_ways);
401 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
402 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
403 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
405 #ifdef CONFIG_SYS_CACHE_STASHING
407 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
409 fdt_setprop_cell(blob, off, "cache-stash-id",
410 (*reg * 2) + 32 + 0);
415 isize = (l1cfg1 & 0x7ff) * 1024;
416 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
417 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
418 inum_sets = isize / (iline_size * inum_ways);
420 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
421 fdt_setprop_cell(blob, off, "i-cache-size", isize);
422 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
424 off = fdt_node_offset_by_prop_value(blob, off,
425 "device_type", "cpu", 4);
428 ft_fixup_l2cache(blob);
432 void fdt_add_enet_stashing(void *fdt)
434 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
436 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
438 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
439 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
440 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
441 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
444 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
445 #ifdef CONFIG_SYS_DPAA_FMAN
446 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
449 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
450 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
453 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
455 printf("WARNING enable to set clock-frequency "
456 "for %s: %s\n", compat, fdt_strerror(off));
461 static void ft_fixup_dpaa_clks(void *blob)
465 get_sys_info(&sysinfo);
466 #ifdef CONFIG_SYS_DPAA_FMAN
467 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
468 sysinfo.freq_fman[0]);
470 #if (CONFIG_SYS_NUM_FMAN == 2)
471 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
472 sysinfo.freq_fman[1]);
476 #ifdef CONFIG_SYS_DPAA_QBMAN
477 do_fixup_by_compat_u32(blob, "fsl,qman",
478 "clock-frequency", sysinfo.freq_qman, 1);
481 #ifdef CONFIG_SYS_DPAA_PME
482 do_fixup_by_compat_u32(blob, "fsl,pme",
483 "clock-frequency", sysinfo.freq_pme, 1);
487 #define ft_fixup_dpaa_clks(x)
491 static void ft_fixup_qe_snum(void *blob)
495 svr = mfspr(SPRN_SVR);
496 if (SVR_SOC_VER(svr) == SVR_8569) {
497 if(IS_SVR_REV(svr, 1, 0))
498 do_fixup_by_compat_u32(blob, "fsl,qe",
499 "fsl,qe-num-snums", 46, 1);
501 do_fixup_by_compat_u32(blob, "fsl,qe",
502 "fsl,qe-num-snums", 76, 1);
507 #if defined(CONFIG_ARCH_P4080)
508 static void fdt_fixup_usb(void *fdt)
510 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
511 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
514 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
515 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
516 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
517 fdt_status_disabled(fdt, off);
519 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
520 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
521 FSL_CORENET_RCWSR11_EC2_USB2)
522 fdt_status_disabled(fdt, off);
525 #define fdt_fixup_usb(x)
528 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
529 defined(CONFIG_ARCH_T4160)
530 void fdt_fixup_dma3(void *blob)
532 /* the 3rd DMA is not functional if SRIO2 is chosen */
534 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
536 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
537 #if defined(CONFIG_ARCH_T2080)
538 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
539 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
540 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
542 switch (srds_prtcl_s2) {
546 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
547 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
548 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
549 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
551 switch (srds_prtcl_s4) {
557 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
558 CONFIG_SYS_ELO3_DMA3);
560 fdt_status_disabled(blob, nodeoff);
562 printf("WARNING: unable to disable dma3\n");
569 #define fdt_fixup_dma3(x)
572 #if defined(CONFIG_ARCH_T1040)
573 static void fdt_fixup_l2_switch(void *blob)
578 /* The l2switch node from device-tree has
579 * compatible string "vitesse-9953" */
580 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
581 if (node == -FDT_ERR_NOTFOUND)
582 /* no l2switch node has been found */
585 /* Get MAC address for the l2switch from "l2switchaddr"*/
586 if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
587 printf("Warning: MAC address for l2switch not found\n");
588 memset(l2swaddr, 0, sizeof(l2swaddr));
591 /* Add MAC address to l2switch node */
592 fdt_setprop(blob, node, "local-mac-address", l2swaddr,
596 #define fdt_fixup_l2_switch(x)
599 void ft_cpu_setup(void *blob, bd_t *bd)
606 /* delete crypto node if not on an E-processor */
607 if (!IS_E_PROCESSOR(get_svr()))
608 fdt_fixup_crypto_node(blob, 0);
609 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
611 ccsr_sec_t __iomem *sec;
613 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
614 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
618 fdt_add_enet_stashing(blob);
620 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
621 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
623 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
624 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
626 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
627 "bus-frequency", bd->bi_busfreq, 1);
628 get_sys_info(&sysinfo);
629 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
630 while (off != -FDT_ERR_NOTFOUND) {
631 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
632 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
633 fdt_setprop(blob, off, "clock-frequency", &val, 4);
634 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
637 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
638 "bus-frequency", bd->bi_busfreq, 1);
642 ft_fixup_qe_snum(blob);
645 #ifdef CONFIG_SYS_DPAA_FMAN
646 fdt_fixup_fman_firmware(blob);
649 #ifdef CONFIG_SYS_NS16550
650 do_fixup_by_compat_u32(blob, "ns16550",
651 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
655 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
656 "current-speed", gd->baudrate, 1);
658 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
659 "clock-frequency", bd->bi_brgfreq, 1);
662 #ifdef CONFIG_FSL_CORENET
663 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
664 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
665 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
666 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
667 do_fixup_by_compat_u32(blob, "fsl,mpic",
668 "clock-frequency", get_bus_freq(0)/2, 1);
670 do_fixup_by_compat_u32(blob, "fsl,mpic",
671 "clock-frequency", get_bus_freq(0), 1);
674 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
677 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
678 ft_fixup_num_cores(blob);
681 ft_fixup_cache(blob);
683 #if defined(CONFIG_FSL_ESDHC)
684 fdt_fixup_esdhc(blob, bd);
687 ft_fixup_dpaa_clks(blob);
689 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
690 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
691 (u64)CONFIG_SYS_BMAN_MEM_PHYS,
692 CONFIG_SYS_BMAN_MEM_SIZE);
693 fdt_fixup_bportals(blob);
696 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
697 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
698 (u64)CONFIG_SYS_QMAN_MEM_PHYS,
699 CONFIG_SYS_QMAN_MEM_SIZE);
701 fdt_fixup_qportals(blob);
704 #ifdef CONFIG_SYS_SRIO
709 * system-clock = CCB clock/2
710 * Here gd->bus_clk = CCB clock
711 * We are using the system clock as 1588 Timer reference
712 * clock source select
714 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
715 "timer-frequency", gd->bus_clk/2, 1);
718 * clock-freq should change to clock-frequency and
719 * flexcan-v1.0 should change to p1010-flexcan respectively
722 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
723 "clock_freq", gd->bus_clk/2, 1);
725 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
726 "clock-frequency", gd->bus_clk/2, 1);
728 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
729 "clock-frequency", gd->bus_clk/2, 1);
733 fdt_fixup_l2_switch(blob);
735 fdt_fixup_dma3(blob);
739 * For some CCSR devices, we only have the virtual address, not the physical
740 * address. This is because we map CCSR as a whole, so we typically don't need
741 * a macro for the physical address of any device within CCSR. In this case,
742 * we calculate the physical address of that device using it's the difference
743 * between the virtual address of the device and the virtual address of the
746 #define CCSR_VIRT_TO_PHYS(x) \
747 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
749 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
751 printf("Warning: U-Boot configured %s at address %llx,\n"
752 "but the device tree has it at %llx\n", name, uaddr, daddr);
756 * Verify the device tree
758 * This function compares several CONFIG_xxx macros that contain physical
759 * addresses with the corresponding nodes in the device tree, to see if
760 * the physical addresses are all correct. For example, if
761 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
762 * of the first UART. We convert this to a physical address and compare
763 * that with the physical address of the first ns16550-compatible node
764 * in the device tree. If they don't match, then we display a warning.
766 * Returns 1 on success, 0 on failure
768 int ft_verify_fdt(void *fdt)
774 /* First check the CCSR base address */
775 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
781 naddr = fdt_address_cells(fdt, off);
782 prop = fdt_getprop(fdt, off, "ranges", &size);
783 addr = fdt_translate_address(fdt, off, prop + naddr);
787 printf("Warning: could not determine base CCSR address in "
789 /* No point in checking anything else */
793 if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
794 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
795 /* No point in checking anything else */
800 * Check some nodes via aliases. We assume that U-Boot and the device
801 * tree enumerate the devices equally. E.g. the first serial port in
802 * U-Boot is the same as "serial0" in the device tree.
804 aliases = fdt_path_offset(fdt, "/aliases");
806 #ifdef CONFIG_SYS_NS16550_COM1
807 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
808 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
812 #ifdef CONFIG_SYS_NS16550_COM2
813 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
814 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
820 * The localbus node is typically a root node, even though the lbc
821 * controller is part of CCSR. If we were to put the lbc node under
822 * the SOC node, then the 'ranges' property in the lbc node would
823 * translate through the 'ranges' property of the parent SOC node, and
824 * we don't want that. Since it's a separate node, it's possible for
825 * the 'reg' property to be wrong, so check it here. For now, we
826 * only check for "fsl,elbc" nodes.
828 #ifdef CONFIG_SYS_LBC_ADDR
829 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
831 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
833 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
835 addr = fdt_translate_address(fdt, off, reg);
837 msg("the localbus", uaddr, addr);
847 void fdt_del_diu(void *blob)
851 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
853 fdt_del_node(blob, nodeoff);