2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_ddr_sdram.h>
13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
17 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
18 unsigned int ctrl_num)
22 ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
24 ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
28 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
32 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
35 out_be32(&ddr->cs0_config, regs->cs[i].config);
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
39 out_be32(&ddr->cs1_config, regs->cs[i].config);
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
43 out_be32(&ddr->cs2_config, regs->cs[i].config);
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
47 out_be32(&ddr->cs3_config, regs->cs[i].config);
51 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
52 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
53 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
54 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
55 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
56 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
57 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
58 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
59 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
60 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
61 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
62 out_be32(&ddr->init_addr, regs->ddr_init_addr);
63 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
66 * 200 painful micro-seconds must elapse between
67 * the DDR clock setup and the DDR config enable.
70 asm volatile("sync;isync");
72 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
74 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
75 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
76 udelay(10000); /* throttle polling rate */