2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/processor.h>
12 #include <asm/fsl_ddr_sdram.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
19 unsigned int ctrl_num, int step)
22 ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
24 #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
25 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
34 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
36 * Set the DDR IO receiver to an acceptable bias point.
40 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
41 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
42 SDRAM_CFG_SDRAM_TYPE_DDR2)
43 out_be32(&gur->ddrioovcr, 0x90000000);
45 out_be32(&gur->ddrioovcr, 0xA8000000);
49 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
51 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
52 out_be32(&ddr->cs0_config, regs->cs[i].config);
55 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
56 out_be32(&ddr->cs1_config, regs->cs[i].config);
59 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
60 out_be32(&ddr->cs2_config, regs->cs[i].config);
63 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
64 out_be32(&ddr->cs3_config, regs->cs[i].config);
68 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
69 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
70 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
71 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
72 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
73 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
74 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
75 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
76 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
77 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
78 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
79 out_be32(&ddr->init_addr, regs->ddr_init_addr);
80 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
83 * 200 painful micro-seconds must elapse between
84 * the DDR clock setup and the DDR config enable.
87 asm volatile("sync;isync");
89 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
91 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
92 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
93 udelay(10000); /* throttle polling rate */