2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <asm/cache.h>
38 #include <asm/fsl_law.h>
39 #include <asm/fsl_serdes.h>
40 #include <asm/fsl_srio.h>
42 #include <linux/compiler.h>
44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
49 #include "../../../../drivers/block/fsl_sata.h"
51 DECLARE_GLOBAL_DATA_PTR;
54 extern qe_iop_conf_t qe_iop_conf_tab[];
55 extern void qe_config_iopin(u8 port, u8 pin, int dir,
56 int open_drain, int assign);
57 extern void qe_init(uint qe_base);
58 extern void qe_reset(void);
60 static void config_qe_ioports(void)
63 int dir, open_drain, assign;
66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
67 port = qe_iop_conf_tab[i].port;
68 pin = qe_iop_conf_tab[i].pin;
69 dir = qe_iop_conf_tab[i].dir;
70 open_drain = qe_iop_conf_tab[i].open_drain;
71 assign = qe_iop_conf_tab[i].assign;
72 qe_config_iopin(port, pin, dir, open_drain, assign);
78 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
82 for (portnum = 0; portnum < 4; portnum++) {
89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
90 iop_conf_t *eiopc = iopc + 32;
95 * index 0 refers to pin 31,
96 * index 31 refers to pin 0
98 while (iopc < eiopc) {
118 volatile ioport_t *iop = ioport_addr (cpm, portnum);
122 * the (somewhat confused) paragraph at the
123 * bottom of page 35-5 warns that there might
124 * be "unknown behaviour" when programming
125 * PSORx and PDIRx, if PPARx = 1, so I
126 * decided this meant I had to disable the
127 * dedicated function first, and enable it
131 iop->psor = (iop->psor & tpmsk) | psor;
132 iop->podr = (iop->podr & tpmsk) | podr;
133 iop->pdat = (iop->pdat & tpmsk) | pdat;
134 iop->pdir = (iop->pdir & tpmsk) | pdir;
141 #ifdef CONFIG_SYS_FSL_CPC
142 static void enable_cpc(void)
147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
150 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
151 size += CPC_CFG0_SZ_K(cpccfg0);
152 #ifdef CONFIG_RAMBOOT_PBL
153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
154 /* find and disable LAW of SRAM */
155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
157 if (law.index == -1) {
158 printf("\nFatal error happened\n");
161 disable_law(law.index);
163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
164 out_be32(&cpc->cpccsr0, 0);
165 out_be32(&cpc->cpcsrcr0, 0);
169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
172 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
176 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
177 /* Read back to sync write */
178 in_be32(&cpc->cpccsr0);
182 printf("Corenet Platform Cache: %d KB enabled\n", size);
185 static void invalidate_cpc(void)
188 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
190 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
191 /* skip CPC when it used as all SRAM */
192 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
194 /* Flash invalidate the CPC and clear all the locks */
195 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
196 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
202 #define invalidate_cpc()
203 #endif /* CONFIG_SYS_FSL_CPC */
206 * Breathe some life into the CPU...
208 * Set up the memory map
209 * initialize a bunch of registers
212 #ifdef CONFIG_FSL_CORENET
213 static void corenet_tb_init(void)
215 volatile ccsr_rcpm_t *rcpm =
216 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
217 volatile ccsr_pic_t *pic =
218 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
219 u32 whoami = in_be32(&pic->whoami);
221 /* Enable the timebase register for this core */
222 out_be32(&rcpm->ctbenrl, (1 << whoami));
226 void cpu_init_f (void)
228 extern void m8560_cpm_reset (void);
229 #ifdef CONFIG_SYS_DCSRBAR_PHYS
230 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
232 #if defined(CONFIG_SECURE_BOOT)
233 struct law_entry law;
235 #ifdef CONFIG_MPC8548
236 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
237 uint svr = get_svr();
240 * CPU2 errata workaround: A core hang possible while executing
241 * a msync instruction and a snoopable transaction from an I/O
242 * master tagged to make quick forward progress is present.
243 * Fixed in silicon rev 2.1.
245 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
246 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
252 #if defined(CONFIG_SECURE_BOOT)
253 /* Disable the LAW created for NOR flash by the PBI commands */
254 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
256 disable_law(law.index);
260 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
263 init_early_memctl_regs();
265 #if defined(CONFIG_CPM2)
269 /* Config QE ioports */
272 #if defined(CONFIG_FSL_DMA)
275 #ifdef CONFIG_FSL_CORENET
278 init_used_tlb_cams();
280 /* Invalidate the CPC before DDR gets enabled */
283 #ifdef CONFIG_SYS_DCSRBAR_PHYS
284 /* set DCSRCR so that DCSR space is 1G */
285 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
286 in_be32(&gur->dcsrcr);
291 /* Implement a dummy function for those platforms w/o SERDES */
292 static void __fsl_serdes__init(void)
296 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
298 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
299 int enable_cluster_l2(void)
303 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
304 struct ccsr_cluster_l2 __iomem *l2cache;
306 cluster = in_be32(&gur->tp_cluster[i].lower);
307 if (cluster & TP_CLUSTER_EOC)
310 /* The first cache has already been set up, so skip it */
313 /* Look through the remaining clusters, and set up their caches */
315 int j, cluster_valid = 0;
317 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
319 cluster = in_be32(&gur->tp_cluster[i].lower);
321 /* check that at least one core/accel is enabled in cluster */
322 for (j = 0; j < 4; j++) {
323 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
324 u32 type = in_be32(&gur->tp_ityp[idx]);
326 if (type & TP_ITYP_AV)
331 /* set stash ID to (cluster) * 2 + 32 + 1 */
332 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
334 printf("enable l2 for cluster %d %p\n", i, l2cache);
336 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
337 while ((in_be32(&l2cache->l2csr0)
338 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
340 out_be32(&l2cache->l2csr0, L2CSR0_L2E);
343 } while (!(cluster & TP_CLUSTER_EOC));
350 * Initialize L2 as cache.
352 * The newer 8548, etc, parts have twice as much cache, but
353 * use the same bit-encoding as the older 8555, etc, parts.
358 __maybe_unused u32 svr = get_svr();
359 #ifdef CONFIG_SYS_LBC_LCRR
360 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
362 #ifdef CONFIG_L2_CACHE
363 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
364 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
365 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
367 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
368 extern int spin_table_compat;
372 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
373 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
375 * CPU22 and NMG_CPU_A011 share the same workaround.
376 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
377 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
378 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
379 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
380 * be disabled by hwconfig with syntax:
382 * fsl_cpu_a011:disable
384 extern int enable_cpu_a011_workaround;
385 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
386 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
388 char buffer[HWCONFIG_BUFFER_SIZE];
392 n = getenv_f("hwconfig", buffer, sizeof(buffer));
396 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
398 enable_cpu_a011_workaround = 0;
400 if (n >= HWCONFIG_BUFFER_SIZE) {
401 printf("fsl_cpu_a011 was not found. hwconfig variable "
402 "may be too long\n");
404 enable_cpu_a011_workaround =
405 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
406 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
409 if (enable_cpu_a011_workaround) {
411 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
416 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
417 spin = getenv("spin_table_compat");
418 if (spin && (*spin == 'n'))
419 spin_table_compat = 0;
421 spin_table_compat = 1;
426 #if defined(CONFIG_L2_CACHE)
427 volatile uint cache_ctl;
431 ver = SVR_SOC_VER(svr);
434 cache_ctl = l2cache->l2ctl;
436 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
437 if (cache_ctl & MPC85xx_L2CTL_L2E) {
438 /* Clear L2 SRAM memory-mapped base address */
439 out_be32(&l2cache->l2srbar0, 0x0);
440 out_be32(&l2cache->l2srbar1, 0x0);
442 /* set MBECCDIS=0, SBECCDIS=0 */
443 clrbits_be32(&l2cache->l2errdis,
444 (MPC85xx_L2ERRDIS_MBECC |
445 MPC85xx_L2ERRDIS_SBECC));
447 /* set L2E=0, L2SRAM=0 */
448 clrbits_be32(&l2cache->l2ctl,
450 MPC85xx_L2CTL_L2SRAM_ENTIRE));
454 l2siz_field = (cache_ctl >> 28) & 0x3;
456 switch (l2siz_field) {
458 printf(" unknown size (0x%08x)\n", cache_ctl);
462 if (ver == SVR_8540 || ver == SVR_8560 ||
463 ver == SVR_8541 || ver == SVR_8555) {
465 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
466 cache_ctl = 0xc4000000;
469 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
473 if (ver == SVR_8540 || ver == SVR_8560 ||
474 ver == SVR_8541 || ver == SVR_8555) {
476 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
477 cache_ctl = 0xc8000000;
480 /* set L2E=1, L2I=1, & L2SRAM=0 */
481 cache_ctl = 0xc0000000;
486 /* set L2E=1, L2I=1, & L2SRAM=0 */
487 cache_ctl = 0xc0000000;
491 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
492 puts("already enabled");
493 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
494 u32 l2srbar = l2cache->l2srbar0;
495 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
496 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
497 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
498 l2cache->l2srbar0 = l2srbar;
499 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
501 #endif /* CONFIG_SYS_INIT_L2_ADDR */
505 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
509 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
510 if (SVR_SOC_VER(svr) == SVR_P2040) {
515 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
517 /* invalidate the L2 cache */
518 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
519 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
522 #ifdef CONFIG_SYS_CACHE_STASHING
523 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
524 mtspr(SPRN_L2CSR1, (32 + 1));
527 /* enable the cache */
528 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
530 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
531 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
533 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
537 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
538 if (l2cache->l2csr0 & L2CSR0_L2E)
539 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
548 /* needs to be in ram since code uses global static vars */
551 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
552 if (IS_SVR_REV(svr, 1, 0)) {
554 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
556 for (i = 0; i < 12; i++) {
557 p += i + (i > 5 ? 11 : 0);
560 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
565 #ifdef CONFIG_SYS_SRIO
567 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
568 char *s = getenv("bootmaster");
570 if (!strcmp(s, "SRIO1")) {
572 srio_boot_master_release_slave(1);
574 if (!strcmp(s, "SRIO2")) {
576 srio_boot_master_release_slave(2);
582 #if defined(CONFIG_MP)
586 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
588 if (SVR_MAJ(svr) < 3) {
590 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
591 setbits_be32(p, 1 << (31 - 14));
596 #ifdef CONFIG_SYS_LBC_LCRR
598 * Modify the CLKDIV field of LCRR register to improve the writing
599 * speed for NOR flash.
601 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
602 __raw_readl(&lbc->lcrr);
604 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
609 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
611 ccsr_usb_phy_t *usb_phy1 =
612 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
613 out_be32(&usb_phy1->usb_enable_override,
614 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
617 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
619 ccsr_usb_phy_t *usb_phy2 =
620 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
621 out_be32(&usb_phy2->usb_enable_override,
622 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
626 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
627 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
628 * multi-bit ECC errors which has impact on performance, so software
629 * should disable all ECC reporting from USB1 and USB2.
631 if (IS_SVR_REV(get_svr(), 1, 0)) {
632 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
633 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
634 setbits_be32(&dcfg->ecccr1,
635 (DCSR_DCFG_ECC_DISABLE_USB1 |
636 DCSR_DCFG_ECC_DISABLE_USB2));
640 #ifdef CONFIG_FMAN_ENET
644 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
646 * For P1022/1013 Rev1.0 silicon, after power on SATA host
647 * controller is configured in legacy mode instead of the
648 * expected enterprise mode. Software needs to clear bit[28]
649 * of HControl register to change to enterprise mode from
650 * legacy mode. We assume that the controller is offline.
652 if (IS_SVR_REV(svr, 1, 0) &&
653 ((SVR_SOC_VER(svr) == SVR_P1022) ||
654 (SVR_SOC_VER(svr) == SVR_P1013))) {
657 /* first SATA controller */
658 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
659 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
661 /* second SATA controller */
662 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
663 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
671 extern void setup_ivors(void);
673 void arch_preboot_os(void)
678 * We are changing interrupt offsets and are about to boot the OS so
679 * we need to make sure we disable all async interrupts. EE is already
680 * disabled by the time we get called.
683 msr &= ~(MSR_ME|MSR_CE);
689 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
690 int sata_initialize(void)
692 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
693 return __sata_initialize();
699 void cpu_secondary_init_r(void)
702 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
703 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
705 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
707 /* load QE firmware from NAND flash to DDR first */
708 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
709 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
711 if (ret && ret == -EUCLEAN) {
712 printf ("NAND read for QE firmware at offset %x failed %d\n",
713 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);