2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <asm/cache.h>
38 #include <asm/fsl_law.h>
39 #include <asm/fsl_serdes.h>
40 #include <asm/fsl_srio.h>
42 #include <linux/compiler.h>
44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
49 #include "../../../../drivers/block/fsl_sata.h"
51 DECLARE_GLOBAL_DATA_PTR;
54 extern qe_iop_conf_t qe_iop_conf_tab[];
55 extern void qe_config_iopin(u8 port, u8 pin, int dir,
56 int open_drain, int assign);
57 extern void qe_init(uint qe_base);
58 extern void qe_reset(void);
60 static void config_qe_ioports(void)
63 int dir, open_drain, assign;
66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
67 port = qe_iop_conf_tab[i].port;
68 pin = qe_iop_conf_tab[i].pin;
69 dir = qe_iop_conf_tab[i].dir;
70 open_drain = qe_iop_conf_tab[i].open_drain;
71 assign = qe_iop_conf_tab[i].assign;
72 qe_config_iopin(port, pin, dir, open_drain, assign);
78 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
82 for (portnum = 0; portnum < 4; portnum++) {
89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
90 iop_conf_t *eiopc = iopc + 32;
95 * index 0 refers to pin 31,
96 * index 31 refers to pin 0
98 while (iopc < eiopc) {
118 volatile ioport_t *iop = ioport_addr (cpm, portnum);
122 * the (somewhat confused) paragraph at the
123 * bottom of page 35-5 warns that there might
124 * be "unknown behaviour" when programming
125 * PSORx and PDIRx, if PPARx = 1, so I
126 * decided this meant I had to disable the
127 * dedicated function first, and enable it
131 iop->psor = (iop->psor & tpmsk) | psor;
132 iop->podr = (iop->podr & tpmsk) | podr;
133 iop->pdat = (iop->pdat & tpmsk) | pdat;
134 iop->pdir = (iop->pdir & tpmsk) | pdir;
141 #ifdef CONFIG_SYS_FSL_CPC
142 static void enable_cpc(void)
147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
150 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
151 size += CPC_CFG0_SZ_K(cpccfg0);
152 #ifdef CONFIG_RAMBOOT_PBL
153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
154 /* find and disable LAW of SRAM */
155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
157 if (law.index == -1) {
158 printf("\nFatal error happened\n");
161 disable_law(law.index);
163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
164 out_be32(&cpc->cpccsr0, 0);
165 out_be32(&cpc->cpcsrcr0, 0);
169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
172 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
176 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
177 /* Read back to sync write */
178 in_be32(&cpc->cpccsr0);
182 printf("Corenet Platform Cache: %d KB enabled\n", size);
185 static void invalidate_cpc(void)
188 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
190 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
191 /* skip CPC when it used as all SRAM */
192 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
194 /* Flash invalidate the CPC and clear all the locks */
195 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
196 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
202 #define invalidate_cpc()
203 #endif /* CONFIG_SYS_FSL_CPC */
206 * Breathe some life into the CPU...
208 * Set up the memory map
209 * initialize a bunch of registers
212 #ifdef CONFIG_FSL_CORENET
213 static void corenet_tb_init(void)
215 volatile ccsr_rcpm_t *rcpm =
216 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
217 volatile ccsr_pic_t *pic =
218 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
219 u32 whoami = in_be32(&pic->whoami);
221 /* Enable the timebase register for this core */
222 out_be32(&rcpm->ctbenrl, (1 << whoami));
226 void cpu_init_f (void)
228 extern void m8560_cpm_reset (void);
229 #ifdef CONFIG_SYS_DCSRBAR_PHYS
230 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
232 #if defined(CONFIG_SECURE_BOOT)
233 struct law_entry law;
235 #ifdef CONFIG_MPC8548
236 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
237 uint svr = get_svr();
240 * CPU2 errata workaround: A core hang possible while executing
241 * a msync instruction and a snoopable transaction from an I/O
242 * master tagged to make quick forward progress is present.
243 * Fixed in silicon rev 2.1.
245 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
246 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
252 #if defined(CONFIG_SECURE_BOOT)
253 /* Disable the LAW created for NOR flash by the PBI commands */
254 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
256 disable_law(law.index);
260 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
263 init_early_memctl_regs();
265 #if defined(CONFIG_CPM2)
269 /* Config QE ioports */
272 #if defined(CONFIG_FSL_DMA)
275 #ifdef CONFIG_FSL_CORENET
278 init_used_tlb_cams();
280 /* Invalidate the CPC before DDR gets enabled */
283 #ifdef CONFIG_SYS_DCSRBAR_PHYS
284 /* set DCSRCR so that DCSR space is 1G */
285 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
286 in_be32(&gur->dcsrcr);
291 /* Implement a dummy function for those platforms w/o SERDES */
292 static void __fsl_serdes__init(void)
296 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
298 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
299 int enable_cluster_l2(void)
303 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
304 struct ccsr_cluster_l2 __iomem *l2cache;
306 cluster = in_be32(&gur->tp_cluster[i].lower);
307 if (cluster & TP_CLUSTER_EOC)
310 /* The first cache has already been set up, so skip it */
313 /* Look through the remaining clusters, and set up their caches */
315 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
316 cluster = in_be32(&gur->tp_cluster[i].lower);
318 /* set stash ID to (cluster) * 2 + 32 + 1 */
319 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
321 printf("enable l2 for cluster %d %p\n", i, l2cache);
323 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
324 while ((in_be32(&l2cache->l2csr0) &
325 (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
327 out_be32(&l2cache->l2csr0, L2CSR0_L2E);
329 } while (!(cluster & TP_CLUSTER_EOC));
336 * Initialize L2 as cache.
338 * The newer 8548, etc, parts have twice as much cache, but
339 * use the same bit-encoding as the older 8555, etc, parts.
344 __maybe_unused u32 svr = get_svr();
345 #ifdef CONFIG_SYS_LBC_LCRR
346 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
348 #ifdef CONFIG_L2_CACHE
349 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
350 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
351 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
354 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
355 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
357 * CPU22 and NMG_CPU_A011 share the same workaround.
358 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
359 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
360 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
361 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
362 * be disabled by hwconfig with syntax:
364 * fsl_cpu_a011:disable
366 extern int enable_cpu_a011_workaround;
367 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
368 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
370 char buffer[HWCONFIG_BUFFER_SIZE];
374 n = getenv_f("hwconfig", buffer, sizeof(buffer));
378 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
380 enable_cpu_a011_workaround = 0;
382 if (n >= HWCONFIG_BUFFER_SIZE) {
383 printf("fsl_cpu_a011 was not found. hwconfig variable "
384 "may be too long\n");
386 enable_cpu_a011_workaround =
387 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
388 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
391 if (enable_cpu_a011_workaround) {
393 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
400 #if defined(CONFIG_L2_CACHE)
401 volatile uint cache_ctl;
405 ver = SVR_SOC_VER(svr);
408 cache_ctl = l2cache->l2ctl;
410 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
411 if (cache_ctl & MPC85xx_L2CTL_L2E) {
412 /* Clear L2 SRAM memory-mapped base address */
413 out_be32(&l2cache->l2srbar0, 0x0);
414 out_be32(&l2cache->l2srbar1, 0x0);
416 /* set MBECCDIS=0, SBECCDIS=0 */
417 clrbits_be32(&l2cache->l2errdis,
418 (MPC85xx_L2ERRDIS_MBECC |
419 MPC85xx_L2ERRDIS_SBECC));
421 /* set L2E=0, L2SRAM=0 */
422 clrbits_be32(&l2cache->l2ctl,
424 MPC85xx_L2CTL_L2SRAM_ENTIRE));
428 l2siz_field = (cache_ctl >> 28) & 0x3;
430 switch (l2siz_field) {
432 printf(" unknown size (0x%08x)\n", cache_ctl);
436 if (ver == SVR_8540 || ver == SVR_8560 ||
437 ver == SVR_8541 || ver == SVR_8555) {
439 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
440 cache_ctl = 0xc4000000;
443 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
447 if (ver == SVR_8540 || ver == SVR_8560 ||
448 ver == SVR_8541 || ver == SVR_8555) {
450 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
451 cache_ctl = 0xc8000000;
454 /* set L2E=1, L2I=1, & L2SRAM=0 */
455 cache_ctl = 0xc0000000;
460 /* set L2E=1, L2I=1, & L2SRAM=0 */
461 cache_ctl = 0xc0000000;
465 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
466 puts("already enabled");
467 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
468 u32 l2srbar = l2cache->l2srbar0;
469 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
470 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
471 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
472 l2cache->l2srbar0 = l2srbar;
473 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
475 #endif /* CONFIG_SYS_INIT_L2_ADDR */
479 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
483 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
484 if (SVR_SOC_VER(svr) == SVR_P2040) {
489 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
491 /* invalidate the L2 cache */
492 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
493 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
496 #ifdef CONFIG_SYS_CACHE_STASHING
497 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
498 mtspr(SPRN_L2CSR1, (32 + 1));
501 /* enable the cache */
502 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
504 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
505 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
507 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
511 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
512 if (l2cache->l2csr0 & L2CSR0_L2E)
513 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
522 /* needs to be in ram since code uses global static vars */
525 #ifdef CONFIG_SYS_SRIO
527 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
528 char *s = getenv("bootmaster");
530 if (!strcmp(s, "SRIO1")) {
532 srio_boot_master_release_slave(1);
534 if (!strcmp(s, "SRIO2")) {
536 srio_boot_master_release_slave(2);
542 #if defined(CONFIG_MP)
546 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
548 if (SVR_MAJ(svr) < 3) {
550 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
551 setbits_be32(p, 1 << (31 - 14));
556 #ifdef CONFIG_SYS_LBC_LCRR
558 * Modify the CLKDIV field of LCRR register to improve the writing
559 * speed for NOR flash.
561 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
562 __raw_readl(&lbc->lcrr);
564 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
569 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
571 ccsr_usb_phy_t *usb_phy1 =
572 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
573 out_be32(&usb_phy1->usb_enable_override,
574 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
577 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
579 ccsr_usb_phy_t *usb_phy2 =
580 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
581 out_be32(&usb_phy2->usb_enable_override,
582 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
586 #ifdef CONFIG_FMAN_ENET
590 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
592 * For P1022/1013 Rev1.0 silicon, after power on SATA host
593 * controller is configured in legacy mode instead of the
594 * expected enterprise mode. Software needs to clear bit[28]
595 * of HControl register to change to enterprise mode from
596 * legacy mode. We assume that the controller is offline.
598 if (IS_SVR_REV(svr, 1, 0) &&
599 ((SVR_SOC_VER(svr) == SVR_P1022) ||
600 (SVR_SOC_VER(svr) == SVR_P1013))) {
603 /* first SATA controller */
604 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
605 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
607 /* second SATA controller */
608 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
609 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
617 extern void setup_ivors(void);
619 void arch_preboot_os(void)
624 * We are changing interrupt offsets and are about to boot the OS so
625 * we need to make sure we disable all async interrupts. EE is already
626 * disabled by the time we get called.
629 msr &= ~(MSR_ME|MSR_CE);
635 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
636 int sata_initialize(void)
638 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
639 return __sata_initialize();
645 void cpu_secondary_init_r(void)
648 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
649 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
651 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
653 /* load QE firmware from NAND flash to DDR first */
654 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
655 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
657 if (ret && ret == -EUCLEAN) {
658 printf ("NAND read for QE firmware at offset %x failed %d\n",
659 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);