2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <asm/fsl_law.h>
37 #include <asm/fsl_serdes.h>
40 DECLARE_GLOBAL_DATA_PTR;
43 extern void fsl_serdes_init(void);
47 extern qe_iop_conf_t qe_iop_conf_tab[];
48 extern void qe_config_iopin(u8 port, u8 pin, int dir,
49 int open_drain, int assign);
50 extern void qe_init(uint qe_base);
51 extern void qe_reset(void);
53 static void config_qe_ioports(void)
56 int dir, open_drain, assign;
59 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
60 port = qe_iop_conf_tab[i].port;
61 pin = qe_iop_conf_tab[i].pin;
62 dir = qe_iop_conf_tab[i].dir;
63 open_drain = qe_iop_conf_tab[i].open_drain;
64 assign = qe_iop_conf_tab[i].assign;
65 qe_config_iopin(port, pin, dir, open_drain, assign);
71 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
75 for (portnum = 0; portnum < 4; portnum++) {
82 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
83 iop_conf_t *eiopc = iopc + 32;
88 * index 0 refers to pin 31,
89 * index 31 refers to pin 0
91 while (iopc < eiopc) {
111 volatile ioport_t *iop = ioport_addr (cpm, portnum);
115 * the (somewhat confused) paragraph at the
116 * bottom of page 35-5 warns that there might
117 * be "unknown behaviour" when programming
118 * PSORx and PDIRx, if PPARx = 1, so I
119 * decided this meant I had to disable the
120 * dedicated function first, and enable it
124 iop->psor = (iop->psor & tpmsk) | psor;
125 iop->podr = (iop->podr & tpmsk) | podr;
126 iop->pdat = (iop->pdat & tpmsk) | pdat;
127 iop->pdir = (iop->pdir & tpmsk) | pdir;
135 * Breathe some life into the CPU...
137 * Set up the memory map
138 * initialize a bunch of registers
141 #ifdef CONFIG_FSL_CORENET
142 static void corenet_tb_init(void)
144 volatile ccsr_rcpm_t *rcpm =
145 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
146 volatile ccsr_pic_t *pic =
147 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
148 u32 whoami = in_be32(&pic->whoami);
150 /* Enable the timebase register for this core */
151 out_be32(&rcpm->ctbenrl, (1 << whoami));
155 void cpu_init_f (void)
157 volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
158 extern void m8560_cpm_reset (void);
159 #ifdef CONFIG_MPC8548
160 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
161 uint svr = get_svr();
164 * CPU2 errata workaround: A core hang possible while executing
165 * a msync instruction and a snoopable transaction from an I/O
166 * master tagged to make quick forward progress is present.
167 * Fixed in silicon rev 2.1.
169 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
170 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
177 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
180 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
181 * addresses - these have to be modified later when FLASH size
182 * has been determined
184 #if defined(CONFIG_SYS_OR0_REMAP)
185 out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
187 #if defined(CONFIG_SYS_OR1_REMAP)
188 out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
191 /* now restrict to preliminary range */
192 /* if cs1 is already set via debugger, leave cs0/cs1 alone */
193 if (! memctl->br1 & 1) {
194 #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
195 out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
196 out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
199 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
200 out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
201 out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
205 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
206 out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
207 out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
210 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
211 out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
212 out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
215 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
216 out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
217 out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
220 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
221 out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
222 out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
225 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
226 out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
227 out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
230 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
231 out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
232 out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
235 #if defined(CONFIG_CPM2)
239 /* Config QE ioports */
242 #if defined(CONFIG_MPC8536)
245 #if defined(CONFIG_FSL_DMA)
248 #ifdef CONFIG_FSL_CORENET
251 init_used_tlb_cams();
256 * Initialize L2 as cache.
258 * The newer 8548, etc, parts have twice as much cache, but
259 * use the same bit-encoding as the older 8555, etc, parts.
265 #ifdef CONFIG_SYS_LBC_LCRR
266 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
271 #if defined(CONFIG_L2_CACHE)
272 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
273 volatile uint cache_ctl;
279 ver = SVR_SOC_VER(svr);
282 cache_ctl = l2cache->l2ctl;
284 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
285 if (cache_ctl & MPC85xx_L2CTL_L2E) {
286 /* Clear L2 SRAM memory-mapped base address */
287 out_be32(&l2cache->l2srbar0, 0x0);
288 out_be32(&l2cache->l2srbar1, 0x0);
290 /* set MBECCDIS=0, SBECCDIS=0 */
291 clrbits_be32(&l2cache->l2errdis,
292 (MPC85xx_L2ERRDIS_MBECC |
293 MPC85xx_L2ERRDIS_SBECC));
295 /* set L2E=0, L2SRAM=0 */
296 clrbits_be32(&l2cache->l2ctl,
298 MPC85xx_L2CTL_L2SRAM_ENTIRE));
302 l2siz_field = (cache_ctl >> 28) & 0x3;
304 switch (l2siz_field) {
306 printf(" unknown size (0x%08x)\n", cache_ctl);
310 if (ver == SVR_8540 || ver == SVR_8560 ||
311 ver == SVR_8541 || ver == SVR_8541_E ||
312 ver == SVR_8555 || ver == SVR_8555_E) {
314 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
315 cache_ctl = 0xc4000000;
318 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
322 if (ver == SVR_8540 || ver == SVR_8560 ||
323 ver == SVR_8541 || ver == SVR_8541_E ||
324 ver == SVR_8555 || ver == SVR_8555_E) {
326 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
327 cache_ctl = 0xc8000000;
330 /* set L2E=1, L2I=1, & L2SRAM=0 */
331 cache_ctl = 0xc0000000;
336 /* set L2E=1, L2I=1, & L2SRAM=0 */
337 cache_ctl = 0xc0000000;
341 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
342 puts("already enabled");
343 l2srbar = l2cache->l2srbar0;
344 #ifdef CONFIG_SYS_INIT_L2_ADDR
345 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
346 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
347 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
348 l2cache->l2srbar0 = l2srbar;
349 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
351 #endif /* CONFIG_SYS_INIT_L2_ADDR */
355 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
359 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
360 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
362 /* invalidate the L2 cache */
363 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
364 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
367 #ifdef CONFIG_SYS_CACHE_STASHING
368 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
369 mtspr(SPRN_L2CSR1, (32 + 1));
372 /* enable the cache */
373 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
375 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
376 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
378 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
384 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
389 #if defined(CONFIG_MP)
393 #ifdef CONFIG_SYS_LBC_LCRR
395 * Modify the CLKDIV field of LCRR register to improve the writing
396 * speed for NOR flash.
398 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
399 __raw_readl(&lbc->lcrr);
406 extern void setup_ivors(void);
408 void arch_preboot_os(void)
413 * We are changing interrupt offsets and are about to boot the OS so
414 * we need to make sure we disable all async interrupts. EE is already
415 * disabled by the time we get called.
418 msr &= ~(MSR_ME|MSR_CE|MSR_DE);
424 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
425 int sata_initialize(void)
427 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
428 return __sata_initialize();