2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
36 #include <asm/cache.h>
38 #include <asm/fsl_law.h>
39 #include <asm/fsl_serdes.h>
40 #include <asm/fsl_srio.h>
42 #include <linux/compiler.h>
44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
49 #include "../../../../drivers/block/fsl_sata.h"
51 DECLARE_GLOBAL_DATA_PTR;
54 extern qe_iop_conf_t qe_iop_conf_tab[];
55 extern void qe_config_iopin(u8 port, u8 pin, int dir,
56 int open_drain, int assign);
57 extern void qe_init(uint qe_base);
58 extern void qe_reset(void);
60 static void config_qe_ioports(void)
63 int dir, open_drain, assign;
66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
67 port = qe_iop_conf_tab[i].port;
68 pin = qe_iop_conf_tab[i].pin;
69 dir = qe_iop_conf_tab[i].dir;
70 open_drain = qe_iop_conf_tab[i].open_drain;
71 assign = qe_iop_conf_tab[i].assign;
72 qe_config_iopin(port, pin, dir, open_drain, assign);
78 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
82 for (portnum = 0; portnum < 4; portnum++) {
89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
90 iop_conf_t *eiopc = iopc + 32;
95 * index 0 refers to pin 31,
96 * index 31 refers to pin 0
98 while (iopc < eiopc) {
118 volatile ioport_t *iop = ioport_addr (cpm, portnum);
122 * the (somewhat confused) paragraph at the
123 * bottom of page 35-5 warns that there might
124 * be "unknown behaviour" when programming
125 * PSORx and PDIRx, if PPARx = 1, so I
126 * decided this meant I had to disable the
127 * dedicated function first, and enable it
131 iop->psor = (iop->psor & tpmsk) | psor;
132 iop->podr = (iop->podr & tpmsk) | podr;
133 iop->pdat = (iop->pdat & tpmsk) | pdat;
134 iop->pdir = (iop->pdir & tpmsk) | pdir;
141 #ifdef CONFIG_SYS_FSL_CPC
142 static void enable_cpc(void)
147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
150 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
151 size += CPC_CFG0_SZ_K(cpccfg0);
152 #ifdef CONFIG_RAMBOOT_PBL
153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
154 /* find and disable LAW of SRAM */
155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
157 if (law.index == -1) {
158 printf("\nFatal error happened\n");
161 disable_law(law.index);
163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
164 out_be32(&cpc->cpccsr0, 0);
165 out_be32(&cpc->cpcsrcr0, 0);
169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
172 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
175 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
176 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
179 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
180 /* Read back to sync write */
181 in_be32(&cpc->cpccsr0);
185 printf("Corenet Platform Cache: %d KB enabled\n", size);
188 static void invalidate_cpc(void)
191 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
193 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
194 /* skip CPC when it used as all SRAM */
195 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
197 /* Flash invalidate the CPC and clear all the locks */
198 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
199 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
205 #define invalidate_cpc()
206 #endif /* CONFIG_SYS_FSL_CPC */
209 * Breathe some life into the CPU...
211 * Set up the memory map
212 * initialize a bunch of registers
215 #ifdef CONFIG_FSL_CORENET
216 static void corenet_tb_init(void)
218 volatile ccsr_rcpm_t *rcpm =
219 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
220 volatile ccsr_pic_t *pic =
221 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
222 u32 whoami = in_be32(&pic->whoami);
224 /* Enable the timebase register for this core */
225 out_be32(&rcpm->ctbenrl, (1 << whoami));
229 void cpu_init_f (void)
231 extern void m8560_cpm_reset (void);
232 #ifdef CONFIG_SYS_DCSRBAR_PHYS
233 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
235 #if defined(CONFIG_SECURE_BOOT)
236 struct law_entry law;
238 #ifdef CONFIG_MPC8548
239 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
240 uint svr = get_svr();
243 * CPU2 errata workaround: A core hang possible while executing
244 * a msync instruction and a snoopable transaction from an I/O
245 * master tagged to make quick forward progress is present.
246 * Fixed in silicon rev 2.1.
248 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
249 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
255 #if defined(CONFIG_SECURE_BOOT)
256 /* Disable the LAW created for NOR flash by the PBI commands */
257 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
259 disable_law(law.index);
263 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
266 init_early_memctl_regs();
268 #if defined(CONFIG_CPM2)
272 /* Config QE ioports */
275 #if defined(CONFIG_FSL_DMA)
278 #ifdef CONFIG_FSL_CORENET
281 init_used_tlb_cams();
283 /* Invalidate the CPC before DDR gets enabled */
286 #ifdef CONFIG_SYS_DCSRBAR_PHYS
287 /* set DCSRCR so that DCSR space is 1G */
288 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
289 in_be32(&gur->dcsrcr);
294 /* Implement a dummy function for those platforms w/o SERDES */
295 static void __fsl_serdes__init(void)
299 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
301 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
302 int enable_cluster_l2(void)
306 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
307 struct ccsr_cluster_l2 __iomem *l2cache;
309 cluster = in_be32(&gur->tp_cluster[i].lower);
310 if (cluster & TP_CLUSTER_EOC)
313 /* The first cache has already been set up, so skip it */
316 /* Look through the remaining clusters, and set up their caches */
318 int j, cluster_valid = 0;
320 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
322 cluster = in_be32(&gur->tp_cluster[i].lower);
324 /* check that at least one core/accel is enabled in cluster */
325 for (j = 0; j < 4; j++) {
326 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
327 u32 type = in_be32(&gur->tp_ityp[idx]);
329 if (type & TP_ITYP_AV)
334 /* set stash ID to (cluster) * 2 + 32 + 1 */
335 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
337 printf("enable l2 for cluster %d %p\n", i, l2cache);
339 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
340 while ((in_be32(&l2cache->l2csr0)
341 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
343 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
346 } while (!(cluster & TP_CLUSTER_EOC));
353 * Initialize L2 as cache.
355 * The newer 8548, etc, parts have twice as much cache, but
356 * use the same bit-encoding as the older 8555, etc, parts.
361 __maybe_unused u32 svr = get_svr();
362 #ifdef CONFIG_SYS_LBC_LCRR
363 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
365 #ifdef CONFIG_L2_CACHE
366 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
367 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
368 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
370 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
371 extern int spin_table_compat;
375 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
376 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
378 * CPU22 and NMG_CPU_A011 share the same workaround.
379 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
380 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
381 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
382 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
383 * be disabled by hwconfig with syntax:
385 * fsl_cpu_a011:disable
387 extern int enable_cpu_a011_workaround;
388 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
389 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
391 char buffer[HWCONFIG_BUFFER_SIZE];
395 n = getenv_f("hwconfig", buffer, sizeof(buffer));
399 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
401 enable_cpu_a011_workaround = 0;
403 if (n >= HWCONFIG_BUFFER_SIZE) {
404 printf("fsl_cpu_a011 was not found. hwconfig variable "
405 "may be too long\n");
407 enable_cpu_a011_workaround =
408 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
409 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
412 if (enable_cpu_a011_workaround) {
414 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
419 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
420 spin = getenv("spin_table_compat");
421 if (spin && (*spin == 'n'))
422 spin_table_compat = 0;
424 spin_table_compat = 1;
429 #if defined(CONFIG_L2_CACHE)
430 volatile uint cache_ctl;
434 ver = SVR_SOC_VER(svr);
437 cache_ctl = l2cache->l2ctl;
439 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
440 if (cache_ctl & MPC85xx_L2CTL_L2E) {
441 /* Clear L2 SRAM memory-mapped base address */
442 out_be32(&l2cache->l2srbar0, 0x0);
443 out_be32(&l2cache->l2srbar1, 0x0);
445 /* set MBECCDIS=0, SBECCDIS=0 */
446 clrbits_be32(&l2cache->l2errdis,
447 (MPC85xx_L2ERRDIS_MBECC |
448 MPC85xx_L2ERRDIS_SBECC));
450 /* set L2E=0, L2SRAM=0 */
451 clrbits_be32(&l2cache->l2ctl,
453 MPC85xx_L2CTL_L2SRAM_ENTIRE));
457 l2siz_field = (cache_ctl >> 28) & 0x3;
459 switch (l2siz_field) {
461 printf(" unknown size (0x%08x)\n", cache_ctl);
465 if (ver == SVR_8540 || ver == SVR_8560 ||
466 ver == SVR_8541 || ver == SVR_8555) {
468 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
469 cache_ctl = 0xc4000000;
472 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
476 if (ver == SVR_8540 || ver == SVR_8560 ||
477 ver == SVR_8541 || ver == SVR_8555) {
479 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
480 cache_ctl = 0xc8000000;
483 /* set L2E=1, L2I=1, & L2SRAM=0 */
484 cache_ctl = 0xc0000000;
489 /* set L2E=1, L2I=1, & L2SRAM=0 */
490 cache_ctl = 0xc0000000;
494 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
495 puts("already enabled");
496 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
497 u32 l2srbar = l2cache->l2srbar0;
498 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
499 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
500 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
501 l2cache->l2srbar0 = l2srbar;
502 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
504 #endif /* CONFIG_SYS_INIT_L2_ADDR */
508 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
512 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
513 if (SVR_SOC_VER(svr) == SVR_P2040) {
518 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
520 /* invalidate the L2 cache */
521 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
522 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
525 #ifdef CONFIG_SYS_CACHE_STASHING
526 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
527 mtspr(SPRN_L2CSR1, (32 + 1));
530 /* enable the cache */
531 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
533 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
534 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
536 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
540 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
541 if (l2cache->l2csr0 & L2CSR0_L2E)
542 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
551 /* needs to be in ram since code uses global static vars */
554 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
555 if (IS_SVR_REV(svr, 1, 0)) {
557 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
559 for (i = 0; i < 12; i++) {
560 p += i + (i > 5 ? 11 : 0);
563 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
568 #ifdef CONFIG_SYS_SRIO
570 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
571 char *s = getenv("bootmaster");
573 if (!strcmp(s, "SRIO1")) {
575 srio_boot_master_release_slave(1);
577 if (!strcmp(s, "SRIO2")) {
579 srio_boot_master_release_slave(2);
585 #if defined(CONFIG_MP)
589 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
591 if (SVR_MAJ(svr) < 3) {
593 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
594 setbits_be32(p, 1 << (31 - 14));
599 #ifdef CONFIG_SYS_LBC_LCRR
601 * Modify the CLKDIV field of LCRR register to improve the writing
602 * speed for NOR flash.
604 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
605 __raw_readl(&lbc->lcrr);
607 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
612 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
614 ccsr_usb_phy_t *usb_phy1 =
615 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
616 out_be32(&usb_phy1->usb_enable_override,
617 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
620 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
622 ccsr_usb_phy_t *usb_phy2 =
623 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
624 out_be32(&usb_phy2->usb_enable_override,
625 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
629 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
630 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
631 * multi-bit ECC errors which has impact on performance, so software
632 * should disable all ECC reporting from USB1 and USB2.
634 if (IS_SVR_REV(get_svr(), 1, 0)) {
635 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
636 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
637 setbits_be32(&dcfg->ecccr1,
638 (DCSR_DCFG_ECC_DISABLE_USB1 |
639 DCSR_DCFG_ECC_DISABLE_USB2));
643 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
644 ccsr_usb_phy_t *usb_phy =
645 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
646 setbits_be32(&usb_phy->pllprg[1],
647 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
648 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
649 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
650 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
651 setbits_be32(&usb_phy->port1.ctrl,
652 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
653 setbits_be32(&usb_phy->port1.drvvbuscfg,
654 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
655 setbits_be32(&usb_phy->port1.pwrfltcfg,
656 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
657 setbits_be32(&usb_phy->port2.ctrl,
658 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
659 setbits_be32(&usb_phy->port2.drvvbuscfg,
660 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
661 setbits_be32(&usb_phy->port2.pwrfltcfg,
662 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
665 #ifdef CONFIG_FMAN_ENET
669 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
671 * For P1022/1013 Rev1.0 silicon, after power on SATA host
672 * controller is configured in legacy mode instead of the
673 * expected enterprise mode. Software needs to clear bit[28]
674 * of HControl register to change to enterprise mode from
675 * legacy mode. We assume that the controller is offline.
677 if (IS_SVR_REV(svr, 1, 0) &&
678 ((SVR_SOC_VER(svr) == SVR_P1022) ||
679 (SVR_SOC_VER(svr) == SVR_P1013))) {
682 /* first SATA controller */
683 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
684 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
686 /* second SATA controller */
687 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
688 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
696 extern void setup_ivors(void);
698 void arch_preboot_os(void)
703 * We are changing interrupt offsets and are about to boot the OS so
704 * we need to make sure we disable all async interrupts. EE is already
705 * disabled by the time we get called.
708 msr &= ~(MSR_ME|MSR_CE);
714 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
715 int sata_initialize(void)
717 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
718 return __sata_initialize();
724 void cpu_secondary_init_r(void)
727 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
728 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
730 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
732 /* load QE firmware from NAND flash to DDR first */
733 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
734 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
736 if (ret && ret == -EUCLEAN) {
737 printf ("NAND read for QE firmware at offset %x failed %d\n",
738 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);