1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003 Motorola Inc.
6 * Modified by Xianghua Xiao, X.Xiao@motorola.com
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
15 #include <asm/processor.h>
20 #include <asm/cache.h>
22 #include <fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
26 #ifdef CONFIG_FSL_CORENET
27 #include <asm/fsl_portals.h>
28 #include <asm/fsl_liodn.h>
29 #include <fsl_qbman.h>
33 #include <linux/compiler.h>
35 #ifdef CONFIG_CHAIN_OF_TRUST
36 #include <fsl_validate.h>
38 #ifdef CONFIG_FSL_CAAM
41 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
42 #include <asm/fsl_pamu.h>
43 #include <fsl_secboot_err.h>
45 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
49 #ifndef CONFIG_ARCH_QEMU_E500
52 #include "../../../../drivers/ata/fsl_sata.h"
57 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
59 * For deriving usb clock from 100MHz sysclk, reference divisor is set
60 * to a value of 5, which gives an intermediate value 20(100/5). The
61 * multiplication factor integer is set to 24, which when multiplied to
62 * above intermediate value provides clock for usb ip.
64 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
68 get_sys_info(&sysinfo);
69 if (sysinfo.diff_sysclk == 1) {
70 clrbits_be32(&usb_phy->pllprg[1],
71 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
72 setbits_be32(&usb_phy->pllprg[1],
73 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
74 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
75 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
80 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
81 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
83 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
84 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
86 /* Increase Disconnect Threshold by 50mV */
87 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
88 INC_DCNT_THRESHOLD_50MV;
89 /* Enable programming of USB High speed Disconnect threshold */
90 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
91 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
93 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
94 /* Increase Disconnect Threshold by 50mV */
95 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
96 INC_DCNT_THRESHOLD_50MV;
97 /* Enable programming of USB High speed Disconnect threshold */
98 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
99 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
103 u32 status = in_be32(&usb_phy->status1);
105 u32 squelch_prog_rd_0_2 =
106 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
107 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
109 u32 squelch_prog_rd_3_5 =
110 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
111 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
113 setbits_be32(&usb_phy->config1,
114 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
115 setbits_be32(&usb_phy->config2,
116 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
118 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
119 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
121 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
122 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
128 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
129 extern qe_iop_conf_t qe_iop_conf_tab[];
130 extern void qe_config_iopin(u8 port, u8 pin, int dir,
131 int open_drain, int assign);
132 extern void qe_init(uint qe_base);
133 extern void qe_reset(void);
135 static void config_qe_ioports(void)
138 int dir, open_drain, assign;
141 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
142 port = qe_iop_conf_tab[i].port;
143 pin = qe_iop_conf_tab[i].pin;
144 dir = qe_iop_conf_tab[i].dir;
145 open_drain = qe_iop_conf_tab[i].open_drain;
146 assign = qe_iop_conf_tab[i].assign;
147 qe_config_iopin(port, pin, dir, open_drain, assign);
153 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
157 for (portnum = 0; portnum < 4; portnum++) {
164 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
165 iop_conf_t *eiopc = iopc + 32;
170 * index 0 refers to pin 31,
171 * index 31 refers to pin 0
173 while (iopc < eiopc) {
193 volatile ioport_t *iop = ioport_addr (cpm, portnum);
197 * the (somewhat confused) paragraph at the
198 * bottom of page 35-5 warns that there might
199 * be "unknown behaviour" when programming
200 * PSORx and PDIRx, if PPARx = 1, so I
201 * decided this meant I had to disable the
202 * dedicated function first, and enable it
206 iop->psor = (iop->psor & tpmsk) | psor;
207 iop->podr = (iop->podr & tpmsk) | podr;
208 iop->pdat = (iop->pdat & tpmsk) | pdat;
209 iop->pdir = (iop->pdir & tpmsk) | pdir;
216 #ifdef CONFIG_SYS_FSL_CPC
217 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
218 void disable_cpc_sram(void)
222 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
224 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
225 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
226 /* find and disable LAW of SRAM */
227 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
229 if (law.index == -1) {
230 printf("\nFatal error happened\n");
233 disable_law(law.index);
235 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
236 out_be32(&cpc->cpccsr0, 0);
237 out_be32(&cpc->cpcsrcr0, 0);
243 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
245 #error POST memory test cannot be enabled with TDM
247 static void enable_tdm_law(void)
250 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
251 int tdm_hwconfig_enabled = 0;
254 * Extract hwconfig from environment since environment
255 * is not setup properly yet. Search for tdm entry in
258 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
260 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
261 /* If tdm is defined in hwconfig, set law for tdm workaround */
262 if (tdm_hwconfig_enabled)
263 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
269 void enable_cpc(void)
275 char buffer[HWCONFIG_BUFFER_SIZE];
277 bool have_hwconfig = false;
279 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
281 /* Extract hwconfig from environment */
282 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
285 * If "en_cpc" is not defined in hwconfig then by default all
286 * cpcs are enable. If this config is defined then individual
287 * cpcs which have to be enabled should also be defined.
288 * e.g en_cpc:cpc1,cpc2;
290 if (hwconfig_f("en_cpc", buffer))
291 have_hwconfig = true;
294 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
296 sprintf(cpc_subarg, "cpc%u", i + 1);
297 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
301 cpccfg0 = in_be32(&cpc->cpccfg0);
302 size += CPC_CFG0_SZ_K(cpccfg0);
304 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
305 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
307 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
308 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
310 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
311 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
313 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
314 if (has_erratum_a006379()) {
315 setbits_be32(&cpc->cpchdbcr0,
316 CPC_HDBCR0_SPLRU_LEVEL_EN);
320 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
321 /* Read back to sync write */
322 in_be32(&cpc->cpccsr0);
326 puts("Corenet Platform Cache: ");
327 print_size(size * 1024, " enabled\n");
330 static void invalidate_cpc(void)
333 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
335 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
336 /* skip CPC when it used as all SRAM */
337 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
339 /* Flash invalidate the CPC and clear all the locks */
340 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
341 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
347 #define invalidate_cpc()
348 #define disable_cpc_sram()
349 #endif /* CONFIG_SYS_FSL_CPC */
352 * Breathe some life into the CPU...
354 * Set up the memory map
355 * initialize a bunch of registers
358 #ifdef CONFIG_FSL_CORENET
359 static void corenet_tb_init(void)
361 volatile ccsr_rcpm_t *rcpm =
362 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
363 volatile ccsr_pic_t *pic =
364 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
365 u32 whoami = in_be32(&pic->whoami);
367 /* Enable the timebase register for this core */
368 out_be32(&rcpm->ctbenrl, (1 << whoami));
372 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
373 void fsl_erratum_a007212_workaround(void)
375 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
377 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
378 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
379 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
380 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
381 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
382 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
383 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
384 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
385 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
389 * Even this workaround applies to selected version of SoCs, it is
390 * safe to apply to all versions, with the limitation of odd ratios.
391 * If RCW has disabled DDR PLL, we have to apply this workaround,
392 * otherwise DDR will not work.
394 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
395 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
396 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
397 /* check if RCW sets ratio to 0, required by this workaround */
398 if (ddr_pll_ratio != 0)
400 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
401 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
402 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
403 /* check if reserved bits have the desired ratio */
404 if (ddr_pll_ratio == 0) {
405 printf("Error: Unknown DDR PLL ratio!\n");
410 setbits_be32(plldadcr1, 0x02000001);
411 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
412 setbits_be32(plldadcr2, 0x02000001);
413 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
414 setbits_be32(plldadcr3, 0x02000001);
417 setbits_be32(dpdovrcr4, 0xe0000000);
418 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
419 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
420 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
421 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
422 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
426 clrbits_be32(plldadcr1, 0x02000001);
427 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
428 clrbits_be32(plldadcr2, 0x02000001);
429 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
430 clrbits_be32(plldadcr3, 0x02000001);
433 clrbits_be32(dpdovrcr4, 0xe0000000);
437 ulong cpu_init_f(void)
439 extern void m8560_cpm_reset (void);
440 #ifdef CONFIG_SYS_DCSRBAR_PHYS
441 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
443 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
444 struct law_entry law;
446 #ifdef CONFIG_ARCH_MPC8548
447 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
448 uint svr = get_svr();
451 * CPU2 errata workaround: A core hang possible while executing
452 * a msync instruction and a snoopable transaction from an I/O
453 * master tagged to make quick forward progress is present.
454 * Fixed in silicon rev 2.1.
456 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
457 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
463 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
464 /* Disable the LAW created for NOR flash by the PBI commands */
465 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
467 disable_law(law.index);
469 #if defined(CONFIG_SYS_CPC_REINIT_F)
475 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
478 init_early_memctl_regs();
480 #if defined(CONFIG_CPM2)
484 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
485 /* Config QE ioports */
489 #if defined(CONFIG_FSL_DMA)
492 #ifdef CONFIG_FSL_CORENET
495 init_used_tlb_cams();
497 /* Invalidate the CPC before DDR gets enabled */
500 #ifdef CONFIG_SYS_DCSRBAR_PHYS
501 /* set DCSRCR so that DCSR space is 1G */
502 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
503 in_be32(&gur->dcsrcr);
506 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
507 fsl_erratum_a007212_workaround();
513 /* Implement a dummy function for those platforms w/o SERDES */
514 static void __fsl_serdes__init(void)
518 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
520 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
521 int enable_cluster_l2(void)
524 u32 cluster, svr = get_svr();
525 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
526 struct ccsr_cluster_l2 __iomem *l2cache;
528 /* only the L2 of first cluster should be enabled as expected on T4080,
529 * but there is no EOC in the first cluster as HW sake, so return here
530 * to skip enabling L2 cache of the 2nd cluster.
532 if (SVR_SOC_VER(svr) == SVR_T4080)
535 cluster = in_be32(&gur->tp_cluster[i].lower);
536 if (cluster & TP_CLUSTER_EOC)
539 /* The first cache has already been set up, so skip it */
542 /* Look through the remaining clusters, and set up their caches */
544 int j, cluster_valid = 0;
546 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
548 cluster = in_be32(&gur->tp_cluster[i].lower);
550 /* check that at least one core/accel is enabled in cluster */
551 for (j = 0; j < 4; j++) {
552 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
553 u32 type = in_be32(&gur->tp_ityp[idx]);
555 if ((type & TP_ITYP_AV) &&
556 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
561 /* set stash ID to (cluster) * 2 + 32 + 1 */
562 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
564 printf("enable l2 for cluster %d %p\n", i, l2cache);
566 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
567 while ((in_be32(&l2cache->l2csr0)
568 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
570 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
573 } while (!(cluster & TP_CLUSTER_EOC));
580 * Initialize L2 as cache.
582 int l2cache_init(void)
584 __maybe_unused u32 svr = get_svr();
585 #ifdef CONFIG_L2_CACHE
586 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
587 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
588 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
593 #if defined(CONFIG_L2_CACHE)
594 volatile uint cache_ctl;
598 ver = SVR_SOC_VER(svr);
601 cache_ctl = l2cache->l2ctl;
603 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
604 if (cache_ctl & MPC85xx_L2CTL_L2E) {
605 /* Clear L2 SRAM memory-mapped base address */
606 out_be32(&l2cache->l2srbar0, 0x0);
607 out_be32(&l2cache->l2srbar1, 0x0);
609 /* set MBECCDIS=0, SBECCDIS=0 */
610 clrbits_be32(&l2cache->l2errdis,
611 (MPC85xx_L2ERRDIS_MBECC |
612 MPC85xx_L2ERRDIS_SBECC));
614 /* set L2E=0, L2SRAM=0 */
615 clrbits_be32(&l2cache->l2ctl,
617 MPC85xx_L2CTL_L2SRAM_ENTIRE));
621 l2siz_field = (cache_ctl >> 28) & 0x3;
623 switch (l2siz_field) {
625 printf(" unknown size (0x%08x)\n", cache_ctl);
629 if (ver == SVR_8540 || ver == SVR_8560 ||
630 ver == SVR_8541 || ver == SVR_8555) {
632 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
633 cache_ctl = 0xc4000000;
636 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
640 if (ver == SVR_8540 || ver == SVR_8560 ||
641 ver == SVR_8541 || ver == SVR_8555) {
643 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
644 cache_ctl = 0xc8000000;
647 /* set L2E=1, L2I=1, & L2SRAM=0 */
648 cache_ctl = 0xc0000000;
653 /* set L2E=1, L2I=1, & L2SRAM=0 */
654 cache_ctl = 0xc0000000;
658 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
659 puts("already enabled");
660 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
661 u32 l2srbar = l2cache->l2srbar0;
662 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
663 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
664 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
665 l2cache->l2srbar0 = l2srbar;
666 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
668 #endif /* CONFIG_SYS_INIT_L2_ADDR */
672 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
676 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
677 if (SVR_SOC_VER(svr) == SVR_P2040) {
682 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
684 /* invalidate the L2 cache */
685 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
686 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
689 #ifdef CONFIG_SYS_CACHE_STASHING
690 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
691 mtspr(SPRN_L2CSR1, (32 + 1));
694 /* enable the cache */
695 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
697 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
698 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
700 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
704 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
705 if (l2cache->l2csr0 & L2CSR0_L2E)
706 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
719 * The newer 8548, etc, parts have twice as much cache, but
720 * use the same bit-encoding as the older 8555, etc, parts.
725 __maybe_unused u32 svr = get_svr();
726 #ifdef CONFIG_SYS_LBC_LCRR
727 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
729 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
730 extern int spin_table_compat;
733 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
734 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
736 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
737 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
739 * CPU22 and NMG_CPU_A011 share the same workaround.
740 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
741 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
742 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
743 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
744 * be disabled by hwconfig with syntax:
746 * fsl_cpu_a011:disable
748 extern int enable_cpu_a011_workaround;
749 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
750 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
752 char buffer[HWCONFIG_BUFFER_SIZE];
756 n = env_get_f("hwconfig", buffer, sizeof(buffer));
760 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
762 enable_cpu_a011_workaround = 0;
764 if (n >= HWCONFIG_BUFFER_SIZE) {
765 printf("fsl_cpu_a011 was not found. hwconfig variable "
766 "may be too long\n");
768 enable_cpu_a011_workaround =
769 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
770 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
773 if (enable_cpu_a011_workaround) {
775 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
780 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
782 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
786 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
788 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
789 * in write shadow mode. Checking DCWS before setting SPR 976.
791 if (mfspr(L1CSR2) & L1CSR2_DCWS)
792 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
795 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
796 spin = env_get("spin_table_compat");
797 if (spin && (*spin == 'n'))
798 spin_table_compat = 0;
800 spin_table_compat = 1;
803 #ifdef CONFIG_FSL_CORENET
805 #ifdef CONFIG_SYS_DPAA_QBMAN
806 setup_qbman_portals();
811 #if defined(CONFIG_RAMBOOT_PBL)
815 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
819 #ifndef CONFIG_SYS_FSL_NO_SERDES
820 /* needs to be in ram since code uses global static vars */
824 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
825 #define MCFGR_AXIPIPE 0x000000f0
826 if (IS_SVR_REV(svr, 1, 0))
827 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
830 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
831 if (IS_SVR_REV(svr, 1, 0)) {
833 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
835 for (i = 0; i < 12; i++) {
836 p += i + (i > 5 ? 11 : 0);
839 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
844 #ifdef CONFIG_SYS_SRIO
846 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
847 char *s = env_get("bootmaster");
849 if (!strcmp(s, "SRIO1")) {
851 srio_boot_master_release_slave(1);
853 if (!strcmp(s, "SRIO2")) {
855 srio_boot_master_release_slave(2);
861 #if defined(CONFIG_MP)
865 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
867 if (SVR_MAJ(svr) < 3) {
869 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
870 setbits_be32(p, 1 << (31 - 14));
875 #ifdef CONFIG_SYS_LBC_LCRR
877 * Modify the CLKDIV field of LCRR register to improve the writing
878 * speed for NOR flash.
880 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
881 __raw_readl(&lbc->lcrr);
883 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
888 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
890 struct ccsr_usb_phy __iomem *usb_phy1 =
891 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
892 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
893 if (has_erratum_a006261())
894 fsl_erratum_a006261_workaround(usb_phy1);
896 out_be32(&usb_phy1->usb_enable_override,
897 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
900 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
902 struct ccsr_usb_phy __iomem *usb_phy2 =
903 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
904 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
905 if (has_erratum_a006261())
906 fsl_erratum_a006261_workaround(usb_phy2);
908 out_be32(&usb_phy2->usb_enable_override,
909 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
913 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
914 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
915 * multi-bit ECC errors which has impact on performance, so software
916 * should disable all ECC reporting from USB1 and USB2.
918 if (IS_SVR_REV(get_svr(), 1, 0)) {
919 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
920 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
921 setbits_be32(&dcfg->ecccr1,
922 (DCSR_DCFG_ECC_DISABLE_USB1 |
923 DCSR_DCFG_ECC_DISABLE_USB2));
927 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
928 struct ccsr_usb_phy __iomem *usb_phy =
929 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
930 setbits_be32(&usb_phy->pllprg[1],
931 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
932 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
933 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
934 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
935 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
936 usb_single_source_clk_configure(usb_phy);
938 setbits_be32(&usb_phy->port1.ctrl,
939 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
940 setbits_be32(&usb_phy->port1.drvvbuscfg,
941 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
942 setbits_be32(&usb_phy->port1.pwrfltcfg,
943 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
944 setbits_be32(&usb_phy->port2.ctrl,
945 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
946 setbits_be32(&usb_phy->port2.drvvbuscfg,
947 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
948 setbits_be32(&usb_phy->port2.pwrfltcfg,
949 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
951 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
952 if (has_erratum_a006261())
953 fsl_erratum_a006261_workaround(usb_phy);
956 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
958 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
959 erratum_a009942_check_cpo();
962 #ifdef CONFIG_FMAN_ENET
966 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
968 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
971 #ifdef CONFIG_FSL_CAAM
974 #if defined(CONFIG_ARCH_C29X)
975 if ((SVR_SOC_VER(svr) == SVR_C292) ||
976 (SVR_SOC_VER(svr) == SVR_C293))
979 if (SVR_SOC_VER(svr) == SVR_C293)
984 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
986 * For P1022/1013 Rev1.0 silicon, after power on SATA host
987 * controller is configured in legacy mode instead of the
988 * expected enterprise mode. Software needs to clear bit[28]
989 * of HControl register to change to enterprise mode from
990 * legacy mode. We assume that the controller is offline.
992 if (IS_SVR_REV(svr, 1, 0) &&
993 ((SVR_SOC_VER(svr) == SVR_P1022) ||
994 (SVR_SOC_VER(svr) == SVR_P1013))) {
997 /* first SATA controller */
998 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
999 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
1001 /* second SATA controller */
1002 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
1003 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
1007 init_used_tlb_cams();
1012 void arch_preboot_os(void)
1017 * We are changing interrupt offsets and are about to boot the OS so
1018 * we need to make sure we disable all async interrupts. EE is already
1019 * disabled by the time we get called.
1022 msr &= ~(MSR_ME|MSR_CE);
1026 #if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA)
1027 int sata_initialize(void)
1029 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
1030 return __sata_initialize();
1036 void cpu_secondary_init_r(void)
1039 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1040 #elif defined CONFIG_QE
1041 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
1050 #ifdef CONFIG_BOARD_LATE_INIT
1051 int board_late_init(void)
1053 #ifdef CONFIG_CHAIN_OF_TRUST
1054 fsl_setenv_chain_of_trust();